The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.

The present disclosure provides a data mutex filter circuit and a data mutex filtering method. The data mutex filter circuit has a main input terminal and a main output terminal and including a preprocessing sub-circuit and a 1st-stage filter sub-circuit to an Nth-stage filter sub-circuit which are cascaded, N being an integer greater than or equal to 2. The 1st-stage filter sub-circuit has an input terminal coupled to the preprocessing sub-circuit, and the Nth-stage filter sub-circuit has an output terminal coupled to the main output terminal. Each stage of filter sub-circuit is configured to compare whether input data currently received at the main input terminal is the same as history data stored therein, and feed back a comparison result to the preprocessing sub-circuit; the preprocessing sub-circuit outputs corresponding data to the 1st-stage filter sub-circuit according to the comparison result fed back by each stage of filter sub-circuit.

A memory array includes a plurality of column segments, each column segment including a plurality of columns of memory cells, a plurality of sense amplifiers selectively coupled to each column of the plurality of columns of a corresponding column segment, pluralities of first and second reference cells, and a reference current circuit. The reference current circuit generates a reference current based on a first current generated by a first reference cell programmed to a low logical value and a second current generated by a second reference cell programmed to a high logical value. Each sense amplifier generates a mirror current based on the reference current, and a logical value based on a comparison of the mirror current to a cell current received from a memory cell of a column of the plurality of columns of the corresponding column segment.

A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.

In an embodiment, a voltage converter is configured to operate by a succession of operating cycles, each cycle comprising an energy accumulation phase and an energy restitution phase, wherein the converter is further configured to determine a duration of one of the phases by comparing a voltage ramp and a first reference voltage, and wherein a slope of the voltage ramp depends on a sign of a current in an inductor at an end of a previous operating cycle.

A comparator circuit includes a first comparator configured to receive input of an input signal and a comparison target signal to be compared with the input signal, a first output stage including an N-channel transistor having a control terminal to which a first control terminal voltage output from the first comparator is applied, and a first clamp unit configured to limit the first control terminal voltage to be not higher than a first predetermined voltage that is higher than a first threshold voltage of the N-channel transistor but is lower than a first high side voltage output as high level from the first comparator when the first control terminal voltage is not limited.

A system for processing a signal in a signal chain having decentralized embedded power management of components of the signal chain includes an input circuit to generate a measurement signal responsive to a stimulus, where the measurement signal is indicative of a characteristic of the stimulus. The system additionally includes a signal converter circuit coupled to the input circuit to convert the measurement signal to a digital signal according to a timing condition for capturing a sample of the measurement signal. The signal converter includes a control circuit to provide electrical power to the input circuit based on the timing condition and a sampling circuit to capture the sample of the measurement signal responsive to an indicator signal generated by the sensor circuit.

Apparatus and methods for sensing resonant circuit signals to enhance control in a resonant converter are described herein. A buffer circuit coupled in parallel with or across a resonant component (e.g., a transformer) input port avails a buffered primary port signal for use in resonant conversion. The buffered primary port signal is a comprehensive signal including information relating to both input voltage and input power; and it may be used to advantageously enhance switching and power conversion in an inductor-inductor capacitor (LLC) converter. Additionally, the LLC converter uses a sense interface circuit to provide a scaled replica of the buffered primary port signal. In one example the scaled replica can advantageously be used with a secondary side controller to control output power based on the comprehensive information contained within the buffered primary port signal.

A comparator circuit includes a first comparator configured to compare a voltage based on an input voltage with a first reference voltage, a charge/discharge portion configured to switch between charging and discharging of a capacitor based on an output of the first comparator, a second comparator configured to compare a voltage of the capacitor with a second reference voltage, and a control portion. The control portion is configured to, in a case where the voltage of the capacitor is larger than a predetermined value when the charge/discharge portion performs switching from the charging of the capacitor to the discharging thereof, supply a predetermined voltage instead of the voltage based on the input voltage to the first comparator until the voltage of the capacitor becomes smaller than the predetermined value so that the discharging of the capacitor is maintained by the charge/discharge portion.

A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.