Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

A semiconductor device and a method for a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a core transistor having a drain configured to receive a first voltage, and a first dummy device connected to the drain of the core transistor, the first dummy device having a first dummy transistor and a second dummy transistor. Wherein a gate and a source of the first dummy transistor are connected to each other. Wherein a drain of the second dummy transistor is connected to the source of the first dummy transistor. Wherein a gate of the second dummy transistor is connected to the drain of the core transistor.

The present disclosure relates to a bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station, and a mobile station. The bootstrapped switch circuit comprises an output for an output signal, a first input, a switching element configured to couple the output with a signal from the first input, a bootstrapper capacitor configured to drive the switching element, and a second input coupled to the bootstrapper capacitor.

A power supply circuit and an apparatus includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first capacitor, and a second capacitor. In this power supply circuit, one terminal of the first capacitor is connected to one terminal of the second capacitor, the other terminal of the first capacitor is separately connected to a first electrode of the first switching transistor and a first electrode of the second switching transistor, a second electrode of the first switching transistor is connected to a second electrode of the third switching transistor, a second electrode of the second switching transistor is connected to a second electrode of the fourth switching transistor, a third electrode of the first switching transistor is connected to an output node, and a third electrode of the second switching transistor is grounded.

The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (S1) representative of the desired state; and the application of the representative value to said at least one switch.

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.

Proposed is a drive circuit including: a driving NMOS transistor having a source set to a reference potential and a driving PMOS transistor having a source set to a first potential, the driving NMOS transistor and the driving PMOS transistor having a mutually common drain connected to a load; a first bipolar transistor configured to control on/off of the driving PMOS transistor; a first switching element that causes conduction or non-conduction between a gate and the source of the driving NMOS transistor; and a second switching element that causes conduction or non-conduction between a gate and the source of the driving PMOS transistor.

A method and device for adjusting the switching speed of a MOSFET are disclosed. The MOSFET is connected to drive switch, the collector of the drive switch is connected to the grid of the MOSFET through the grid resistor, the emitter of the drive switch is grounded through the emitter resistor, and the collector of the drive switch is also connected to the source resistor through the collector resistor, the other end of the source resistor is connected to the source of the MOSFET; the drain of the MOSFET is connected to the current source. The method comprises: obtaining the adjustment target of the switching speed for the MOSFET, determining the first resistance value of the emitter resistor and/or the second resistance value of the collector resistor based on said adjustment target, controlling the operation of the MOSFET according to the adjusted resistance value.

A driving circuit for a semiconductor circuit which includes a pair of main terminals through which a main current is conducted and a control terminal to which a control voltage is applied to control a circulation state of the main current, includes: driving voltage switching circuitry that receives a control signal, instructs switching between driving voltages based on a change in the control signal, and outputs a driving voltage, among the driving voltages, that has been selected in the switching; low-speed control circuitry that instructs an increase-decrease change in the control voltage at a low speed; speed-increase control circuitry that executes a speed-increase control of increasing a speed of the increase-decrease change made by the low-speed control circuitry; and speed-increase switching circuitry that instructs switching between an execution and a non-execution of the speed-increase control, and instructs switching between levels of a speed-increase change caused by the speed-increase control.

In a switching circuit, an inductance of an inductor of a shunt circuit is such that off capacitance of a second switching device that is in the off state when a first switching device is in the on state is used to define, in the shunt circuit, a series resonance circuit with a desired resonant frequency. Therefore, the frequency of an unnecessary signal to be attenuated is set to the resonant frequency of the series resonance circuit. Thus, the switching circuit achieves improved isolation characteristics with other circuits by attenuating the unnecessary signal.