An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.

A smart control system includes a first unsmart switch disposed in a first electrical outlet box; a second unsmart switch disposed in a second electrical outlet box; and a smart switch electrically connected in series between the first unsmart switch and the second unsmart switch, the smart switch being not disposed in an electrical outlet box.

Power cycle life of an intelligent power module that includes an IGBT is estimated by an abnormality detection circuit(s) while a chip temperature detection circuit or a case temperature detection circuit is outputting a chip overheating warning signal or a case overheating warning signal. Once the estimated power cycle life has reached a prescribed value, the abnormality detection circuit outputs an abnormality detection signal to forcedly and permanently stop operation of a driver circuit that drives an IGBT. The abnormality detection circuit may include a prescribed period calculation circuit that calculates the duration of the warning signal, a prescribed count calculation circuit that calculates the number of times the warning signal has been generated, and/or a cumulative time calculation circuit that calculates that the cumulative duration of periods in which the warning signal has been generated so as to estimate the power cycle life of the intelligent power module.

An apparatus controls a high-power drive device external to a package of a gate driver circuit. A first circuit charges the control node over a first length of time in response to a first signal through the first node indicating an absence of a fault condition and a first level of a control signal. A second circuit discharges the control node over a second length of time in response to a second signal through the second node indicating the absence of the fault condition and a second level of a control signal. A third circuit includes a current amplifier and is configured as a soft shutdown path to discharge the control node over a third length of time in response to the first signal through the first node indicating a presence of the fault condition. The third length of time is different from the second length of time.

Techniques for determining a temperature measurement of a junction of a power switch are described. A current can be applied to a control node, e.g., gate terminal, of the power switch, such as a field-effect transistor (FET) or an insulated-gate bipolar transistor (IGBT), while the power switch is in a steady-state region in which a gate-to-source voltage (e.g., FET) or a gate-to-emitter voltage (e.g., IGBT) of the power switch is constant. While in the steady-state region, the temperature measurements can be performed, thereby ensuring accuracy of the measurement.

A control device includes a first series circuit and a second series circuit. In the first series circuit, a first switch and a first resistor are connected in series to each other. In the second series circuit, a second switch and a second resistor are connected in series to each other. A current detection circuit outputs a voltage value that corresponds to a voltage value between two ends of the first resistor. When an instruction to turn on the first switch and the second switch has been given, a control unit senses any occurrence of a failure in at least one of the first switch, the second switch, the first resistor, and the second resistor, based on the voltage value output by the current detection circuit.

Disclosed is a signal transmission circuit, comprising: a common interface, a first switch, a second switch, and an interference-resistant branch; the common interface is configured to, receive a digital signal through the first switch when the first switch is closed, or to receive an analog signal through the second switch when the second switch is closed; the interference-resistant branch is configured to eliminate an interference of the second switch on the digital signal; a signal input of the interference-resistant branch is configured to receive the digital signal, and a signal output of the interference-resistant branch is connected to a signal input of the first switch; and/or, the signal input of the interference-resistant branch is connected to a signal output of the second switch, and the signal output of the interference-resistant branch is connected to a signal input of the common interface.

A server switch system includes a switch unit and a field-programmable gate array (FPGA) unit. The switch unit includes a first switch interface for receiving the first data and sending the second data, and a second switch interface for sending the third data and receiving the fourth data. The switch unit is used to generate the third data according to the first data, and generate the second data according to the fourth data. The FPGA unit includes an FPGA interface coupled to the second switch interface for receiving the third data from the switch unit and sending the fourth data to the switch unit.

A semiconductor device includes a semiconductor element, a die pad, an encapsulating member, and a plurality of leads. The die pad has a front surface on which the semiconductor element is mounted. The encapsulating member covers and seals the semiconductor element. The plurality of leads each have a first end connected to the semiconductor element in an inside of the encapsulating member and a second end led out from a side surface of the encapsulating member. A lower surface of a package including the semiconductor element, the die pad, and the encapsulating member is located on a back surface side of the die pad and has a convexly curved shape.

A switch having a drain, a source, and a control. The switch comprising a depletion-mode transistor including a first, a second, and a control terminal and an enhancement-mode transistor including a first, a second, and a control terminal. The first terminal of the depletion-mode transistor is the drain of the switch and the control of the depletion-mode transistor is coupled to the source of the switch. The control of the enhancement-mode transistor is coupled to the control of the switch, the second terminal of the enhancement-mode transistor is the source of the switch. The switch comprises a clamp circuit to clamp a voltage of the first terminal of the enhancement-mode transistor to a threshold, the clamp circuit comprises a resistor and a pn-junction device coupled between the first and second terminals of the enhancement-mode transistor and between the second terminal and the control of the depletion-mode transistor.