To provide a semiconductor device signal transmission circuit for drive-control, a method of controlling a semiconductor device signal transmission circuit for drive-control, a semiconductor device, a power conversion device, and an electric system for a railway vehicle capable of preventing malfunction due to noise while speeding up or reducing loss of a switching operation. The semiconductor device signal transmission circuit for drive-control that is connected between a semiconductor device constituting an arm in a power conversion device and a drive circuit configured to drive the semiconductor device, including: an inductor; and an impedance circuit including a switch and connected in parallel with the inductor.

A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

A system including: a first regulator having a first input voltage and a first output voltage; a second regulator having a second input voltage and a second output voltage; a first driver circuit coupled to the first regulator and a switch, wherein the first driver circuit is configured to drive the switch based on the first output voltage; a second driver circuit coupled to the second regulator and the switch, wherein the second driver circuit is configured to drive the switch based on the second output voltage; a driver controller coupled to the first driver circuit and the second driver circuit, wherein the driver controller is configured to select one of the first driver circuit and the second driver circuit to drive the switch based on a control signal; and a switch node coupled to the switch, wherein a switch node voltage at the switch node is a function of the switch being turned on and off.

A driving circuit and a driving method are provided. According to embodiments of the present disclosure, a power switch is driven by constant voltage or constant current during different time periods. The power switch is driven by using a first driving current during a Miller platform period, and the power switch is driven by using a second driving current when the Miller platform period ends, where the first driving current is less than the second driving current, so as to optimize EMI, reduce loss and improve efficiency.

A selection circuit architecture makes it possible to perform upward and/or downward transitions in sets of sequences of slow and fast phases so as at the same time to solve the problems of inductive switching noise and the problems of currents in the supply rails. This solution has multiple advantages linked to the ease of implementation and flexibility of configurations that are possible for adapting to the specific constraints when designing the circuit.

A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

An electronic module includes a power supply wiring line disposed on a substrate along a first side and connected to a power supply terminal, a ground wiring line disposed on the substrate along a second side and connected to a ground terminal, and first to third half bridges each having a high-side switch and a low-side switch connected in series between the power supply wiring line and the ground wiring line. Connection points of the high-side switches and the low-side switches are connected to first to third motor terminals and also connected in parallel to one another. The first motor terminal, the second motor terminal, and the third motor terminal are disposed between the power supply terminal and the ground terminal.

A driver circuit drives an output terminal with an input/output voltage using an NMOS transistor and a PMOS transistor. A pre-driver for the NMOS transistor supplied with a drive voltage and receives a data signal referenced to the drive voltage. A pre-driver for the PMOS transistor has a positive supply input connected to the positive supply rail, a negative supply input receiving a second drive voltage equal to the supply voltage minus the drive voltage. A level shifter circuit, shifts the data signal to be referenced between the supply voltage and the second drive voltage. A charge pump circuit for providing second drive voltage, the charge pump circuit driven with a variable switching frequency proportional to a current of the PMOS transistor.

An integrated circuit for controlling an ignition system including a coil. The integrated circuit includes a transistor configured to control a current flowing through the coil, a first line coupled to a control electrode of the transistor, a second line coupled to an electrode of the transistor on the ground side thereof, a control circuit configured to control on and off of the transistor based on a voltage level of the first line, and a Zener diode having a cathode coupled to the first line and an anode coupled to the second line. The Zener diode has such a capacitance that, when a first signal, and a second signal of a higher frequency, are inputted to the first line, the control circuit controls the on and off of the transistor in response to the first signal irrespective of the second signal.