Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack.

The invention relates to an electrical circuit (1) for transmitting a useful analogue signal, which has a signal transmission path (16) with an input path (2) and an output path (3) and at least one switch (6), with which the useful signal which is carried on the input path (2) can be connected through to the output path (3) or the signal transmission path (16) can be interrupted. According to the invention, a compensation circuit (4) which substantially compensates for a distortion of the useful analogue useful signal generated by the at least one switch (6) when it is switched off (OFF) is provided, wherein the compensation circuit (4) is connected to a control terminal (G) of the at least one switch (6) and comprises at least one non-linear capacitance.

Disclosed is an circuit for preventing latch-up, comprising a first transistor, a second transistor of a type opposite to that of the first transistor, and a control circuit, wherein a control terminal of the first transistor receives a first control voltage and a first terminal of the first transistor receives a first supply voltage; a control terminal of the second transistor receives a second control voltage, and is connected to a second terminal of the first transistor; a first terminal of the second transistor is connected to the control terminal of the first transistor, and a second terminal of the second transistor receives a second supply voltage. The control circuit is coupled on a path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage for disconnecting the path when the first control voltage and/or the second control voltage is out of a predetermined range. The circuit for preventing latch-up provided by the present invention, by introducing the control circuit on the path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, can disconnect the path when the first control voltage and/or the second control voltage is out of the predetermined range, so that a latch-up effect is prevented from occurring during power-on phase.

Switch circuitry is disclosed having a series stack of transistors coupled between first and second port terminals. A string of gate resistors having a common gate terminal is coupled to gates of the series stack of transistors. A bias control transistor has a bias control terminal and first and second current terminals. The second control terminal is coupled to a switch control terminal configured to receive on-state and off-state control voltages that transition the series stack of transistors between passing a radio frequency signal and blocking the radio frequency signal from passing between the first and second port terminals, respectively. A string of diodes is coupled between the common gate terminal and the first current terminal, and a common gate resistor is coupled between the common gate terminal and the switch control terminal. The diodes contribute to actively generating additional negative gate bias as RF power level increases.

In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

A circuit for driving the voltage of a capacitive element between two voltage levels has at least one driver cell with a first pair of switches connected in series between a first terminal of a voltage source and the capacitive element, and a second pair of switches connected in series between a second terminal of the voltage source and the capacitive element. One or more non-dissipative elements may be connected between the common node of the first pair of switches and the common node of the second pair of switches. Combinations of switches from the driver cells may be activated and deactivated in a defined sequence to provide step-wise transfer of energy to the capacitive element. In one sequence, switches in a selected driver cell may subtract a specified voltage from an input voltage, bypass the selected driver cell, and add the specified voltage to the input voltage.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

The invention provides a gate drive device, a gate drive method, a power semiconductor module, and an electric power conversion device capable of reducing a negative gate surge voltage. The gate drive device drives a semiconductor device constituting an arm in an electric power conversion device. Before a turn-off start of a drive arm, in a counter arm, a voltage between one main terminal of the semiconductor device and a gate terminal of the semiconductor device is charged to a voltage value that is larger, in a positive direction, than a negative voltage of a negative gate power supply and smaller than a gate threshold voltage of the semiconductor device.

An electromagnetic interference regulator by use of capacitive parameters of the field-effect transistor for detecting the induced voltage and the induced current of the field-effect transistor to determine whether the operating frequency of the field-effect transistor is within the preset special management frequency of electromagnetic interference. When the basic frequency and the multiplied frequency exceed the limit, the content of the external capacitor unit can be adjusted to assist the products using field-effect transistors to maintain excellent electromagnetic interference adjustment capabilities under various loads, thereby optimizing the characteristics of electromagnetic interference.

A drive circuit includes a second drive circuit that drives a semiconductor switching element in a case where a pulse width of a corresponding signal is determined to be larger than a second threshold, and a timing adjustment circuit that adjusts a timing at which the second drive circuit cooperates with a first drive circuit to drive the semiconductor switching element during a turn-off period of the semiconductor switching element due to drive of the first drive circuit.