Disclosed herein is a power electronic device assembly for preventing parasitic switching-on of a feeder circuit breaker. The assembly includes a logic circuit, a power switch with an input and a reference leg, and a driver circuit which drives the power switch. The driver circuit includes a drive unit and a short circuit having a safety function. When the input of the power switch is not operated, the power switch is short-circuited by the reference leg so that the potential of the input decreases below a switching-on threshold. An additional wire connection device is disposed between the driver circuit and the power switch and configured such that when no or excessively small amount of supply voltage is applied, the input of the power switch is short-circuited or is coupled to a safety potential at which discharge is secured, whereby discharge of parasitic charge current is secured.

A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate (20a) are provided gate lines (13G) and source lines. On the active-matrix substrate (20a) are further provided: gate drivers (11) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line (13G); and lines (15L1) each for supplying a control signal to the associated gate driver (11). A control signal is supplied by a display control circuit (4) located outside the display region to the gate drivers (11) via the lines (15L1). In response to a control signal supplied, each gate driver (11) drives the gate line (13G) to which it is connected.

An electronic switch for connecting units of a power supply system has a semiconductor switch, an actuation circuit and a current/voltage sensor for detecting current flow through the electronic switch. The actuation circuit operates the semiconductor switch, depending on oscillations measured by the current/voltage sensor, in an activated state, a deactivated state or a linear mode. A power supply system having the electronic switch for connecting with the electronic switch two electrical sub-networks and a method for operating the electronic switch are also disclosed. The semiconductor switch is operated at least temporarily in the linear mode for damping oscillations.

A semiconductor device includes: a first field-effect transistor configured to have a source connected to a reference potential node; a second field-effect transistor configured to have a source connected to a drain of the first field-effect transistor, and a gate connected to the source of the first field-effect transistor; a gate signal node configured to input a gate signal therein; a first resistor configured to be connected between the gate signal node and a gate of the first field-effect transistor; and a first capacitor and a switch circuit configured to be connected between a drain of the second field-effect transistor and the gate of the first field-effect transistor, in which the switch circuit is connected in series with the first capacitor.

A doorbell chime bypass circuit includes a first node, a second node, and a bi-directional FET switch in series with the first node and the second current node. The bi-directional FET switch includes a first FET and a second FET in series, and is configured to cease conducting current between the first and second nodes when gate voltages of the first and second FETs are below a cut-off threshold. The bypass circuit further includes a sensing circuit configured to determine a level of current flowing through the bi-directional FET switch, and a switch controller configured to set the gate voltages of the first and second FETs to a level below the cut-off threshold when the sensing circuit senses that the level of current meets a doorbell press current threshold, causing the bi-directional FET switch to cease conducting current between the first and second nodes.

The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

A semiconductor device includes an upper switching element, a lower switching element, an upper capacitor, and a lower capacitor. The upper switching element is formed by a wide-gap semiconductor and includes a first upper terminal, a second upper terminal, and an upper control terminal. The lower switching element is formed by a wide-gap semiconductor and includes a first lower terminal, a second lower terminal, and a lower control terminal. The upper capacitor is provided between the first upper terminal and the upper control terminal separately from the upper switching element. The lower capacitor is provided between the first lower terminal and the lower control terminal separately from the lower switching element. The second upper terminal and the first lower terminal are electrically connected.

A semiconductor device includes an inverter circuit having a first switching element and a second switching element, a first control circuit, a second control circuit, and a limiting unit. The first switching element is supplied with a power supply voltage. The second switching element includes a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal. The first control circuit controls the first switching element. The second control circuit controls the second switching element. The limiting unit reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element.

A power drive circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weighting unit, and a comparator. Each gate driver includes a drive resistance setting value. The waveform processing unit outputs a current absolute value waveform of an AC power. The weighting unit generates a trigger voltage. When the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each of the gate drivers. When the gate driver receives the slew rate control signal, each of the gate drivers decreases the drive resistance setting value of the gate driver.

A switching apparatus (20) comprises first and second current paths, each current path configured to be capable of conducting an electrical current, the first current path including a first switching element (28) connected in parallel with a first passive current check element (30), the switching apparatus (20) further including a switching controller configured to selectively control the switching of the first switching element (28), wherein the switching controller is configured to selectively switch the first switching element (28) at a first intra-current path switching speed to commutate the electrical current between the first switching element (30) and the first passive current check element (32), the switching controller is configured to selectively switch the first switching element (28) at a first inter-current path switching speed to commutate the electrical current between the first and second current paths, and the first intra-current path switching speed is faster or slower than the first inter-current path switching speed.