A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn “closer” to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

Techniques are described for implementing diodes with low threshold voltages and high breakdown voltages. Some embodiments further implement diode devices with programmable threshold voltages. For example, embodiments can couples a native device with one or more low-threshold, diode-connected devices. The coupling is such that the low-threshold device provides a low threshold voltage while being protected from breakdown by the native device, effectively manifesting as a high breakdown voltage. Some implementations include selectable branches by which the native device is programmably coupled with any of multiple low-threshold, diode-connected devices.

Apparatus and methods for providing hot-switching immunity for radio frequency switching circuits are disclosed. A radio frequency switching circuit may include both a mechanical switch and a solid-state switch. The mechanical switch may be configurable to couple an output path of a power amplifier to a subsequent component in its transmission path when in a first mechanical switch state and to decouple the output path of the power amplifier from the subsequent component when in a second mechanical switch state. The solid-state switch may be configurable to operatively decouple the mechanical switch from a radio frequency power source when in a first solid-state switch state but not when in a second solid-state switch state. The solid-state switch may be in the first solid-state switch state during transitions of the mechanical switch between the first and second mechanical switch states.

A power source selection system can include a primary source line configured to be connected to a primary source having a primary voltage, a backup source line configured to connect to a backup source having a backup voltage, and a voltage divider and limiter connected to the primary source line to receive the primary voltage and to provide an sense signal on a sense line. The system can include a NAND gate connected to the voltage divider and limtier to receive the sense signal. The NAND gate can be configured to provide a gate signal to a gate line based on the sense signal. The system can include a switchover circuit connected to the backup source line and the gate line to receive the backup voltage and the gate signal. The switchover circuit can be configured to output the backup voltage to a switch line in a first state, and to prevent backup voltage to the switch line in a second state. The switchover circuit can be configured to switch between the first state and the second state based on the gate signal. The system can include an ORing circuit connected to the primary source line and to the switch line. The ORing circuit can be configured to select between the primary voltage and backup voltage and to output the selected voltage as the output voltage.

A power source selection system can include a primary source line configured to be connected to a primary source having a primary voltage, a backup source line configured to connect to a backup source having a backup voltage, and a voltage divider and limiter connected to the primary source line to receive the primary voltage and to provide an sense signal on a sense line. The system can include a NAND gate connected to the voltage divider and limtier to receive the sense signal. The NAND gate can be configured to provide a gate signal to a gate line based on the sense signal. The system can include a switchover circuit connected to the backup source line and the gate line to receive the backup voltage and the gate signal. The switchover circuit can be configured to output the backup voltage to a switch line in a first state, and to prevent backup voltage to the switch line in a second state. The switchover circuit can be configured to switch between the first state and the second state based on the gate signal. The system can include an ORing circuit connected to the primary source line and to the switch line. The ORing circuit can be configured to select between the primary voltage and backup voltage and to output the selected voltage as the output voltage.

Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.

A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.

A control device includes a triac and a first diode that is series-connected between the triac and a first terminal of the device that is configured to be connected to a cathode gate of a thyristor. A second terminal of the control device is configured to be connected to an anode of the thyristor. The triac has a gate connected to a third terminal of the device that is configured to receive a control signal. The thyristor is a component part of one or more of a rectifying bridge circuit, an in-rush current limiting circuit or a solid-state relay circuit.

Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising a first semiconductor device and a second semiconductor device coupled together in a first anti-series configuration between a first terminal and a second terminal; a third semiconductor device and a fourth semiconductor device coupled together in a second anti-series configuration between the first terminal and the second terminal; a controller configured to operate the power switch to simultaneously conduct a first portion of a load current from the first terminal to the second terminal by closing the first semiconductor device and the second semiconductor device, and to conduct a second portion of the load current from the first terminal to the second terminal by closing the third semiconductor device and the fourth semiconductor device.

Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising a first semiconductor device and a second semiconductor device coupled together in a first anti-series configuration between a first terminal and a second terminal; a third semiconductor device and a fourth semiconductor device coupled together in a second anti-series configuration between the first terminal and the second terminal; a controller configured to operate the power switch to simultaneously conduct a first portion of a load current from the first terminal to the second terminal by closing the first semiconductor device and the second semiconductor device, and to conduct a second portion of the load current from the first terminal to the second terminal by closing the third semiconductor device and the fourth semiconductor device.