A system and method for high speed switching comprises receiving voltage inputs at a bridge rectifier, generating a control signal from a transistor, and driving a gate of a field effect transistor (FET) via the control signal of the transistor, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The system and method further comprises limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.

A system and method for high speed switching comprises receiving voltage inputs at a bridge rectifier, generating a control signal from a transistor, and driving a gate of a field effect transistor (FET) via the control signal of the transistor, wherein a source of the FET is connected to a negative output of the bridge rectifier and a drain of the FET is connected to a positive output of the bridge rectifier through a load. The system and method further comprises limiting current flowing to the gate of the FET through first and second resistors and first and second diodes connecting the voltage inputs to the gate of the FET and limiting voltage to the gate of the FET below a maximum voltage rating of the FET by a Zener diode connected to the gate of the FET.

A power supply circuit includes an inductor, a power transistor configured to control an inductor current flowing through the inductor, and an integrated circuit driving the power transistor. The integrated circuit includes a first terminal that receives a power supply voltage for operating the integrated circuit, generated according to a variation in the inductor current, a second terminal to which a control electrode of the power transistor is coupled, a first drive circuit configured to drive the power transistor via the second terminal during a first time period to turn on the power transistor, and a second drive circuit configured to drive the power transistor via the second terminal during a second time period to turn on the power transistor, the second time period including at least a part of the first time period, driving capability of the second drive circuit being lower than that of the first drive circuit.

According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.

According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.

A semiconductor device includes a light-emitting element, a light-receiving element, an input-side terminal, a first switching element, a first lead and a resin package. The first lead includes a first mount bed and a first output-side terminal, the first switching element being mounted on the first mount bed. The resin package seals the light-emitting element, the light-receiving element, and the first switching element. The resin package includes first and second side surfaces opposite to each other. The input-side terminal protrudes from the first side surface. The first output-side terminal protrudes from the second side surface. The first switching element is sealed at a center between the first and second side surfaces. The first mount bed is arranged in a direction along the second side surface so that a side surface of the first mount bed is positioned between a center of the resin package and the first output-side terminal.

A switching device includes an insulated gate bipolar transistor (IGBT) or MOSFET having a gate, an emitter, and a collector configured to allow current to pass between the emitter and the collector based on voltage applied to the gate. A stack of alternating layers of photo-sensitive p-n junction layers and insulating layers stacked on the gate for optical switching control of voltage through the IGBT or MOSFET.

A switching device includes an insulated gate bipolar transistor (IGBT) or MOSFET having a gate, an emitter, and a collector configured to allow current to pass between the emitter and the collector based on voltage applied to the gate. A stack of alternating layers of photo-sensitive p-n junction layers and insulating layers stacked on the gate for optical switching control of voltage through the IGBT or MOSFET.

A first input circuit is connected to a first input terminal and a second input terminal in a package. A second input circuit is connected to the first input terminal and the third input terminal in the package. A third input circuit is connected to the first or second input terminal and a third input terminal in the package. A first output circuit is connected to a first output terminal and a first connection line in the package. A second output circuit is connected to a second output terminal and the first connection line in the package. A third output circuit is connected to a third output terminal and the first connection line in the package.

A semiconductor relay module includes first to third semiconductor relays, first to third input terminals, first to third output terminals, and a first connection line. A first input circuit of the first semiconductor relay and a second input circuit of the second semiconductor relay are connected to the first and second input terminals. The first and second input circuits are connected in series. A third input circuit of the third semiconductor relay is connected to the first or second input terminal and the third input terminal. A first output circuit of the first semiconductor relay is connected to the first output terminal and the first connection line. A second output circuit of the second semiconductor relay is connected to the second output terminal and the first connection line. A third output circuit of the third semiconductor relay is connected to the third output terminal and the first connection line.