Described is soft error tolerant flip-flop which comprises hardened sequential elements to reduce latch soft error rate. The flip-flop may include a master latch; and a slave latch coupled to the master latch, wherein only one of the master or slave latch of the flip-flop comprises hardened latch circuitry. For example, only the master latch comprises the hardened latch circuitry.

Techniques to compensate non-radiation hardened components for changes or degradation in performance that result from exposure to radiation. During testing and modeling phase, a component's performance may be characterized as a result of the exposure to radiation. In some examples, some performance characteristics, such as voltage response, frequency response, gain, leakage or other characteristics, may change as the component's exposure to an amount of radiation increases. During normal operation, a system may include one or more devices that measure the amount of radiation to which the system may be subjected, such as a radiation dosimeter. The system may compensate the non-radiation hardened component based on the amount of radiation received the known component performance change caused by radiation as determined during the modeling phase.

Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

Described is soft error tolerant flip-flop which comprises hardened sequential elements to reduce latch soft error rate. The flip-flop may include a master latch; and a slave latch coupled to the master latch, wherein only one of the master or slave latch of the flip-flop comprises hardened latch circuitry. For example, only the master latch comprises the hardened latch circuitry.

An apparatus that includes a single event latchup (SEL) recovery circuit, a microprocessor operatively connected with the SEL recovery circuit, and an output maintenance circuit that maintains a state of the microprocessor prior to a power cycle of the microprocessor. The apparatus is configured to detect a SEL event or other fault via a watchdog circuit, initiate a power cycle of the microprocessor, retain a latch state from the microprocessor, and determine whether the microprocessor was restarted due to an SEL event. Responsive to determining that the microprocessor has failed to restart due to a persistent fault, the apparatus determines whether a prepower cycle limit is reached within a predetermined span of time, and selectively provide power to a load based on the latch state and the power cycle limit determination.

Disclosed herein is a circuit including first and second input circuits. The first input circuit is configured to receive first and second logic signals and to source current to first and second control nodes if at least one of the first and second logic signals is at a logic low. The second input circuit is configured to receive the first and second logic signals and to sink current from the first and second control nodes if at least one of the first and second logic signals is at a logic high. A first output circuit is configured to source current to an output node when current is sunk from the first control node. A second output circuit is configured to sink current from the output node when current is sourced to the second control node. A latch is coupled to the output node.

A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.

The present disclosure relates to a radiation-hardened analog-to-digital converter circuit and its digital signal calibration method capable of efficiently compensating for an external influence or a changed semiconductor element performance, and a recording medium for performing the method.

A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

A bi-state driver circuit for switching an output terminal between a first predetermined voltage level and a high impedance state, which involves a first string of transistors connected between the output terminal and the first predetermined voltage level at least a first transistor arranged closer to the first predetermined voltage level, a second transistor arranged closer to the output terminal, a voltage divider circuit connected between the output terminal and a voltage level of a control signal attaining voltage levels between the first predetermined voltage level and a second predetermined voltage level, including at least one intermediate node having an intermediate voltage level between a voltage level of the output terminal and the voltage level of the control signal, and a second string of transistors connected between the intermediate node of the voltage divider circuit and the second predetermined voltage level, and including at least a third transistor.