A leakage compensation dynamic register, a data operation unit, a chip, a hash board, and a computing apparatus. The leakage compensation dynamic register comprises: an input terminal, an output terminal, a clock signal terminal, and an analog switch unit; a data latch unit for latching the data under control of the clock signal; and an output drive unit for inverting and outputting the data received from the data latch unit, the analog switch unit, the data latch unit, and the output drive unit being sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the data latch unit having a node therebetween, wherein the leakage compensation dynamic register further comprises a leakage compensation unit electrically connected between the node and the output terminal.

Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

In embodiments of the invention, the present invention is directed to a contact hearing system, the contact hearing system including: an ear tip, the ear tip including a transmit coil wherein the transmit coil is wound around a core including, at least in part, a ferromagnetic material; and a contact hearing device including a receive coil wherein the receive coil is wound around a core including, at least in part, a non-ferromagnetic material.

Disclosed is a switching circuit including an input terminal, a switching terminal, a grounding terminal, a bootstrap terminal, a high-side transistor connected between the input terminal and the switching terminal, a low-side transistor connected between the switching terminal and the grounding terminal, a bootstrap capacitor connected between the switching terminal and the bootstrap terminal, a bootstrap switch connected between a constant voltage line and the bootstrap terminal, and a driver circuit configured to turn on the bootstrap switch in a period of time in which the low-side transistor is on and to turn off the bootstrap switch in a period of time in which the low-side transistor is off. The bootstrap switch includes two P-channel metal oxide semiconductor transistors connected in anti-series with each other between the constant voltage line and the bootstrap terminal.

In one embodiment, the present invention is directed to a contact hearing system including: an ear tip including a transmit circuit having a first Q value, wherein the ear tip includes a transmit coil wound on a ferrite core; a contact hearing device including a receive circuit having a second Q value, wherein the first Q value is greater than the second Q value; a receive coil positioned on the contact hearing device, wherein the receive coil includes a core of a non-ferromagnetic material.

An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.

Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).

An output driver is provided. The output driver includes: a pull-up driver connected between an output power supply voltage and an output node, and configured to pull up a voltage at the output node based on a pull-up driving signal and a pull-up reference voltage; a pull-down driver connected between the output node and a ground voltage, and configured to pull down the voltage at the output node based on a pull-down driving signal and a pull-down reference voltage; and a reference voltage compensation circuit configured to perform a short operation during transitions of the pull-up driving signal and the pull-down driving signal, wherein the short operation includes electrically connecting any one or any combination of the pull-up reference voltage to the ground voltage, and the pull-down reference voltage to the output power supply voltage.

In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.