The present disclosure discloses a pre-driver circuit and a driving device. The pre-driver circuit includes a first transistor, a second transistor, and a resistive component. The first transistor has a first terminal coupled to a first voltage, a second terminal for outputting a pre-driving signal, and a control terminal for receiving a first control signal. The second transistor has a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to a second voltage, and a control terminal for receiving the first control signal. The resistive component has a first terminal coupled to the first terminal of the second transistor, and a second terminal coupled to the second terminal of the second transistor. One of the first transistor and the second transistor is a P-type transistor, and the other is an N-type transistor.

A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal of a buffer that drives the gate of the cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, a voltage boost is provided to the gates of the cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.

A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a M.sub.x layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the M.sub.x layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a M.sub.y layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the M.sub.y layer that is coupled to the second output on the fifth track.

An apparatus is described. The apparatus includes a stacked switch circuit having protection circuitry to prevent shoot through current when the switch is in an off state and respective voltages at the terminals of the switch change such that before the change one of the terminals of the switch has the higher voltage and after the change the other terminal of the switch has the higher voltage.

Disclosed herein is a signal potential converter which may perform high-speed operation and which may still maintain intended signal amplitude and operate normally even while operating at a low rate or receiving a burst signal. In this signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential at the terminal node, i.e., a signal IN, within the range of a first potential to a second potential. If a potential at the terminal node is higher than a third potential, a voltage holder circuit operates to raise the potential at the terminal node. If the potential at the terminal node is lower than the third potential, the voltage holder circuit operates to lower the potential at the terminal node.

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.

A driver system operable to supply a drive signal to a motor includes a system input adapted to be coupled to an input voltage and a system output adapted to be coupled to the motor. The driver system includes a high-side transistor which has a first terminal coupled to the system input, a second terminal coupled to the system output, and has a control terminal. The driver system includes a low-side transistor which has a first terminal coupled to the system output, a second terminal coupled to a reference potential terminal, and has a control terminal. The driver system includes a low-side gate control circuit which provides a first level current responsive to a low-side digital control signal transitioning from a low state to a high state and provides a second level current if the output voltage is less than an upper reference voltage.

A circuit is disclosed. The circuit includes an output driver with a pull-up device, and a pull-down device. The circuit also includes a pre-driver, configured to generate a first signal for the pull-up device and to generate a second signal for the pull-down device, a first positive feedback circuit configured to increase the slew rate of the first signal in response to a transition in the second signal, and a second positive feedback circuit configured to increase the slew rate of the second signal in response to a transition in the first signal.