The present disclosure provides circuits and methods that can be used to update configurations. An example circuit can include a plurality hLUTs and a plurality of registers configured to propagate a set of data or a portion thereof to the plurality of hLUTs. An hLUT of the plurality of hLUTs can have a transformation unit comprising transformation circuitry configured to (i) receive the set of data or the portion thereof from a register of the plurality of registers and (ii) transform the set of data or the portion thereof into configurations for the hLUT.

In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.

A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

The present disclosure provides an integrated circuit and a computing system. The integrated circuit and a computing system includes a dynamic voltage and frequency scaling (DVFS) operation and a method of operating the integrated circuit. The integrated circuit includes a plurality of sub blocks and a dynamic voltage and frequency scaling (DVFS) controller. The DVFS controller is configured to output a workload of the plurality of sub blocks, determine a first frequency corresponding to the workload, determine a first voltage corresponding to the first frequency, and provide a second frequency among at least one frequency corresponding to the first voltage to the plurality of sub blocks.

A computer system may include a host device including a memory controller and a first interface circuit configured to provide the memory controller with an interface to other devices; and a data storage unit in communication with the host device through a channel and configured to communicate with the host device through a second interface circuit including a termination circuit. The first interface circuit is configured to select between different termination schemes. The first interface circuit is configured to add an addition signal to a transmission signal based on a termination scheme of the termination circuit and transmit the transmission signal with the addition signal to the termination circuit.

Integrated circuit devices are provided. The devices may include a substrate including a first region, a second region and a boundary region between the first and second regions. The first and second regions may be spaced apart from each other in a first horizontal direction. The devices may also include a first latch on the first region, a second latch on the second region, and a conductive layer extending in the first horizontal direction and crossing over the boundary region. The first latch may include a first vertical field effect transistor (VFET), a second VFET, a third VFET, and a fourth VFET. The second latch may include a fifth VFET, a sixth VFET, a seventh VFET, and an eighth VFET. The first and seventh VFETs may be arranged along the first horizontal direction. Portions of the conductive layer may include gate electrodes of the first and seventh VFETs, respectively.

A new computational machine is invented, called a clock machine, that is a novel alternative to computing machines (digital computers) based on logic gates. In an embodiment, computation is performed with one or more clock machines that use time, and can perform any Boolean function. In an embodiment, a cryptographic cipher is implemented with random clock machines, constructed from a non-deterministic process, wherein the compiled set of instructions (i.e., the implementation of the cryptographic procedure) is distinct on each device or chip that executes the cryptographic cipher. In an embodiment, by using a different set of clock machines to execute two different instances of the same cryptographic procedure, each execution of a procedure looks different to malware that may try to infect and subvert the cryptographic procedure. This cryptographic process helps hinder timing attacks. In an embodiment, a detailed implementation of the Midori cipher with random clock machines is described.

Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS); correcting circuits (34, 36) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C2, C3) connected between the control terminals and the input terminal; diode-connected second transistors (35, 37) that are provided between nodes (N5, N6) between the capacitors and the control terminals and the power supply potentials and have the substantially sanle threshold voltage as the first transistors; and switches (SW2, SW3) connected in series with the second transistors.

A multiply-accumulate operation device, circuit and method are disclosed. In on example, a multiply-accumulate operation device includes input lines, multiplication units, an accumulation unit, a charging unit, and an output unit. Pulse signals having pulse widths corresponding to input values are input to the input lines. The multiplication units generate, based on the pulse signals, charges corresponding to multiplication values obtained by multiplying the input values by weight values. The accumulation unit accumulates a sum of the charges corresponding to the multiplication values. The charging unit charges the accumulation unit at a charging speed associated with its accumulation state. The output unit outputs a multiply-accumulate signal representing a sum of the multiplication values by executing threshold determination using a threshold value associated with the accumulation state of the accumulation unit on a voltage held by the accumulation unit after the charging by the charging unit is started.

Embodiments of the present technology provide a synchronous device. The synchronous device provides a first latch configured to store a data input signal during a first state of a first clock signal and a slack guard circuit. The slack guard circuit provides a delay element coupled to the first latch and configured to generate a delayed data signal, a gated-input cell coupled to the delay element and configured to propagate the delayed data signal during the first state of the first clock signal, and a comparator coupled to the first latch and the gated-input cell.