Patent classifications
H03K19/017518
SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate body of a first conductivity-type; a first well region of a second conductivity-type provided in the substrate body and provided with a high-side circuit; a first voltage blocking region of the second conductivity-type provided around the first well region; a contact region of the second conductivity-type provided at an upper part of the first well region or the first voltage blocking region; a second voltage blocking region of the first conductivity-type provided on an outer circumferential side of the first voltage blocking region so as to be in contact with the first voltage blocking region; a first isolation region of the first conductivity-type provided to electrically isolate, from the first well region, an opposed part of the first voltage blocking region opposed to a low-side circuit provided on an outer circumferential side of the second voltage blocking region; and a level shifter.
COMMUNICATION INTERFACE AND METHOD FOR OPERATING A COMMUNICATION INTERFACE
The invention relates to a communication interface between a control unit and an electric load unit, particularly a load unit having a pump motor in a motor vehicle, wherein the control unit is designed as a transmitter and/or receiver, wherein the load unit is designed as a receiver and/or transmitter and wherein the communication between the transmitter and the receiver takes place via a signal line by means of a pulse-width-modulated signal. In this case, there is provision for the signal line to be connected to a constant current source and for the transmitter to be designed to modulate the flow of current through the signal line by means of pulse-width modulation. The invention further relates to a method for operating such a communication interface.
Voltage level translation circuit and multiple interface in communication system
A voltage level translation circuit includes a first energy storage unit, a second energy storage unit, a first voltage level translation unit, and a second voltage level translation unit. The first voltage level translation unit is configured to translate a first communication interface transmitting pin voltage signal to realize a first communication between a first communication interface transmitting pin and a second communication interface receiving pin. The second voltage level translation unit is configured to translate a second communication interface transmitting pin voltage signal to realize a second communication between a second communication interface transmitting pin and a first communication interface receiving pin. A multiple interface communication system is also provided.
Push-pull output driver and operational amplifier using same
A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.
Level shifter circuit
Techniques are disclosed for a level shifter configured to adjust current flow in response to measured current fluctuations due to common mode noise in the level shifter. For example, the level shifter includes a low-side control circuit configured to adjust a first current flowing into a first low-side terminal of an active high voltage level shifter device in response to a difference between the first low-side current and a second low-side current flowing into a second low-side terminal of an inactive high voltage level shifter device. The level shifter further includes a high-side receiver circuit configured to detect a difference between a first high-side current flowing into a first high-side terminal of the active high voltage level shifter device and a second high-side current flowing into a second high-side terminal of the inactive high voltage level shifter device.
TRANSMITTER CIRCUIT AND RECEIVER CIRCUIT FOR OPERATING UNDER LOW VOLTAGE
A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.
Multi-format driver interface
A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.
CONTROL CIRCUIT AND METHOD THEREFOR
In one embodiment, a control circuit may be configured to form a switching signal to switch a power transistor at a frequency to regulate an output voltage of the power supply to a target value wherein the control circuit is configured to operate in a normal operating mode and a start-up mode and wherein the control circuit is configured to switch the switching signal at a target frequency in response to operating in the normal operating mode. A first circuit may be configured to control the frequency of the switching signal to increase from a first frequency to a second frequency that is less than the target frequency in response to operating in the start-up mode.
LEVEL SHIFTER
The present disclosure provides a level shifter including: a level shifter section that is driven by a first power source voltage, and that, in accordance with switching of an input signal of a voltage lower than the first power source voltage, switches an output signal that has been level-shifted, from the first power source voltage to a voltage lower than the first power source voltage; and a threshold voltage changing circuit that, in accordance with a switching direction of the input signal, changes a threshold voltage of the input signal for switching the output signal.
Transmitter circuit and receiver circuit for operating under low voltage
A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.