A repeater for open-drain bus communication and a system including the same is provided. The bus repeater includes an A-to-B buffer to receive the signal at the A-side terminal and to produce a first buffered signal, a B-side pull-down control unit to produce a first control signal based on the received first buffered signal, and a B-side pull-down element to pull down the voltage at the B-side terminal based on the first control signal. The B-side pull-down element includes a B-side pull-down transistor that is arranged in between the B-side terminal and a B-side ground reference terminal. The first control signal controls a voltage at the control terminal of the B-side pull-down transistor. The B-side pull-down control unit includes a B-side comparing unit to compare the voltage at the B-side terminal to a first reference voltage, and to generate the first control signal based on a result of the comparison.

An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

Disclosed herein are related to systems and methods for providing different power supply levels. In one aspect, a first circuit generates a first signal having a first amplitude according to a first supply voltage. A latch may be coupled to a resistor of a plurality of resistors coupled in series. One end of the resistor may be configured to provide to the latch a second supply voltage higher than the first supply voltage according to a third supply voltage higher than the second supply voltage, and another end of the resistor may be configured to receive the third supply voltage. The latch may modify the first signal to provide a second signal, according to the second supply voltage. An amplifier may amplify the second signal to provide a third signal having a second amplitude larger than the first amplitude, according to the third supply voltage.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.

A level shifter circuit, comprising one or more thin gate transistors having source and drain terminals coupled, respectively, to a power supply node and a reference node, where the one or more thin gate transistors have an electrical over stress (EOS) threshold voltage that is lower than a voltage of the power supply applied across two terminals of the one or more thin gate transistors. The circuit further includes a PFET pulldown circuit coupled to an EOS protection circuit to limit the voltage difference across at least two terminals of the one or more thin gate transistors to a voltage below the EOS threshold voltage based on the threshold voltage the PFET.

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

An output driving circuit includes: a plurality of bias voltage generating circuits configured to generate a plurality of bias voltages; a switching control circuit; and an output voltage generating circuit. The switching control circuit is configured to selectively connect one bias voltage generating circuit of the plurality of bias voltage generating circuits to the output voltage generating circuit based on an output voltage. The output voltage generating circuit is configured to transmit and receive a parasitic current generated due to transition of the output voltage to and from the one bias voltage generating circuit selectively connected to the output voltage generating circuit through the switching control circuit.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.