A bidirectional RF circuit, preferably including a plurality of terminals, a switch, a transistor, a coupler, and a feedback network. The circuit can optionally include a drain matching network, an input matching network, and/or one or more tuning inputs. In some variations, the circuit can optionally include one or more impedance networks, such as an impedance network used in place of the feedback network; in some such variations, the circuit may not include a coupler, switch, and/or input matching network. A method for circuit operation, preferably including operating in an amplifier mode, operating in a rectifier mode, and/or transitioning between operation modes.

The disclosure provides a level shifter circuit. The level shifter circuit includes a first transistor and a second transistor. The first transistor and the second transistor generate an output voltage according to a first control signal and a second control signal, respectively. A time interval of rising edges of the output voltage is greater than a time interval of falling edges of the output voltage.

A driver for a shared bus, such as a LIN bus, having a supply node (Vbat), a bus node (LIN), a transmit data input node (TX) and a receive data output node (RX), said driver comprising: a pull-up circuitry between the supply node and the bus node, driver circuitry (100) having a control input connected to the transmit data input node, feedback circuitry (200) configured to provide feedback from the shared bus to the control input of the driver circuitry; said feedback circuitry comprising copy circuitry (210) configured to obtain at least one copy signal representative for a signal on the bus node, filter circuitry (220) configured to low-pass filter the at least one copy signal, derivative circuitry (230) configured to obtain at least one derivative signal representative for the speed at which the signal on the bus node varies.

The series regulator has: a differential amplifier; a level shifter including a level shift transistor with a drain connected to a gate; and a source follower including an output transistor. The differential amplifier includes an amplification stage having a non-inverting input terminal for input of a reference voltage, an inverting input terminal for input of a feedback voltage, and an amplifier output terminal. The differential amplifier has a DC operation point where an error of an output voltage at the amplifier output terminal to an input voltage to the non-inverting input terminal is equal to or under a gate-source voltage of an input transistor, and a follower output terminal of the source follower is feedback-connected to the inverting input terminal. The level shifter performs a level shift to make an output voltage of the source follower coincident with the voltage at the amplifier output terminal of the differential amplifier.

An apparatus for performing level shift control in an electronic device includes an input stage positioned in a level shifter of the electronic device, and an output stage positioned in the level shifter and coupled to the input stage through a set of intermediate nodes. The input stage is arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of the set of intermediate nodes according to the at least one input signal. The input stage includes a hybrid current control circuit coupled to the at least one input terminal and arranged for performing current control for the input stage. The hybrid current control circuit is equipped with multiple sets of parallel paths for controlling currents passing through the set of intermediate nodes, respectively, each set may include two or more paths in parallel.

A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.

A circuit is disclosed. The circuit includes an output driver with a pull-up device, and a pull-down device. The circuit also includes a pre-driver, configured to generate a first signal for the pull-up device and to generate a second signal for the pull-down device, a first positive feedback circuit configured to increase the slew rate of the first signal in response to a transition in the second signal, and a second positive feedback circuit configured to increase the slew rate of the second signal in response to a transition in the first signal.

A battery-disconnect circuit may include a latch, a battery-disconnect subcircuit, and a power-enable subcircuit. The battery-disconnect subcircuit may be configured to control current leakage. The battery-disconnect subcircuit may be connected to the latch. The latch may be configured to maintain a power supply state of the battery-disconnect subcircuit, a no-power supply state of the battery-disconnect subcircuit, or both. The power-enable subcircuit may be connected to the battery-disconnect subcircuit. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the power supply state based on an enable signal. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the no-power supply state based on an off signal.

A voltage-controlled oscillator is provided. A semiconductor device includes a first circuit and a second circuit. The first circuit has a function of holding a first potential and a function of controlling the level of a third potential supplied to the second circuit according to a second potential based on the first potential. The second circuit has a function of outputting a second signal based on a first signal input to the second circuit. The delay time from input of the first signal to the second circuit to output of the second signal from the second circuit is determined by the third potential.

In a processor or the like including a reconfigurable (RC) circuit, the RC circuit is used to form a test circuit to test a core, a cache memory, or the like, and then part of the RC circuit is used as an auxiliary cache memory. When a memory can store data after stop of power supply, a startup routine program (SRP) of the processor can be stored therein. For example, after the test, an SRP is loaded to a memory in the RC circuit from an external ROM or the like, and when power is resupplied to the processor, a startup operation is performed using the loaded SRP. When the processor is in a normal operation state, this memory is used as an auxiliary cache memory and the SRP is overwritten. The SRP is loaded to the memory again at the end of use of the processor.