An arrangement that includes a bus subscriber with two power supply terminals, at least one bus line terminal and a bus interface circuit for controlling a data flow via the at least one bus line terminal, wherein a controllable switch is located between the bus interface circuit and the at least one bus line terminal and the bus subscriber contains a sensor circuit which records the voltage between the power supply terminals or a voltage derived therefrom and closes the controllable switch if the recorded voltage exceeds a threshold value and opens the same if the recorded voltage fails to reach the threshold value, where with an arrangement including at least two bus subscribers, these bus subscribers are connected with their bus line terminals to a bus having at least one bus line and with their power supply terminals via two current lines to a shared voltage source.

A transmitter according to the disclosure includes: three first driver sections; three first pre-driver sections that are provided corresponding to the respective three first driver sections, and each drive corresponding one of the first driver sections on a basis of corresponding one of three first control signals that are different from one another and each including predetermined number of signals; a second pre-driver section that operates on a basis of a second control signal that includes predetermined number of signals; and a controller that controls transition of the predetermined number of signals included in the second control signal to allow number of signals to be subjected to the transition out of the plurality of signals included in the three first control signals and the plurality of signals included in the second control signal to be same between timings of the transition.

A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.

A signal isolation system includes an external device; and a signal isolation circuit, coupled to the external device, including a control circuit, configured to operate the signal isolation circuit in an input mode or an output mode according to a status of the external device; a digital input/output circuit, configured to input/output signal based on the input mode or the output mode determined by the control circuit; and an input/output port, coupled to the digital input/output circuit, configured to be an input port or an output port according to the input mode or the output mode determined by the control circuit.

A transmitter is provided with a plurality of pull-up legs and a plurality of pull-down legs. A controller controls the pull-up legs and the pull-down legs so that a constant output impedance is provided while supporting a range of logic-high output voltages.

An off chip driver circuit includes a first power rail, a second power rail, an input/output pad, a pull-up circuit, a pull-down circuit. The pull-up circuit is configured to selectively activate at least one of charging paths between the first power rail and the input/output pad. The pull-up circuit includes a first resistor and PMOS transistors arranged on the charging paths, and the first resistor is coupled between the first power rail and the PMOS transistors. The pull-down circuit is configured to selectively activate at least one of discharging paths between the second power rail and the input/output pad. The pull-down circuit includes a second resistor and NMOS transistors arranged on the discharging paths, and the second resistor is coupled between the second power rail and the NMOS transistors.

A transmission device according to the disclosure includes a driver section that is able to transmit a data signal by using three or more predetermined number of voltage states and set voltages in each of the voltage states; and a control section that sets an emphasis voltage that is based on a transition among the predetermined number of the voltage states, and thereby causes the driver section to perform emphasis.