A state-retaining logic cell may include a plurality of inverters, an output node non-volatile (NVM) storage cell, and an input node NVM storage cell. The plurality of inverters may include a feed-forward inverter and a feed-back inverter disposed in a back-to-back arrangement. The output node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an output node of the feed-forward and the feed-back inverters, and the second terminal is connected to a programming rail. The input node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an input node of the feed-forward and the feed-back inverters, and the second terminal is connected to the programming rail.

A state-retaining logic cell may include a plurality of inverters, an output node non-volatile (NVM) storage cell, and an input node NVM storage cell. The plurality of inverters may include a feed-forward inverter and a feed-back inverter disposed in a back-to-back arrangement. The output node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an output node of the feed-forward and the feed-back inverters, and the second terminal is connected to a programming rail. The input node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an input node of the feed-forward and the feed-back inverters, and the second terminal is connected to the programming rail.

An integrated circuit (IC) includes a first circuit that is powered by a first supply voltage, and a second circuit that is powered by a second supply voltage. The second supply voltage has a lower level than the first supply voltage. The IC further includes a power management circuit. The power management circuit includes a switch-mode DC-DC regulator that is coupled to a plurality of pins of the IC in a pre-defined configuration. The power management circuit provides the first and second supply voltages to power up the IC in a default configuration without knowledge of the pre-defined configuration.

Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

A novel programmable logic device is provided. Programmable switches each include a first transistor and a second transistor. The first transistor in a first programmable switch controls conduction between a first wiring and a gate of the second transistor in the first programmable switch. The second transistor in the first programmable switch controls conduction between the first wiring and a second wiring. The first transistor in the second programmable switch controls conduction between another first wiring and a gate of the second transistor in the second programmable switch.

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.