A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

The various embodiments described herein include methods, devices, and systems for implementing logic gates. In one aspect, a circuit includes: (1) a superconducting component having a plurality of alternating narrow and wide portions; (2) a plurality of heat sources, each heat source of the plurality of heat sources coupled to a corresponding narrow portion of the plurality of alternating narrow and wide portions and configured to selectively provide heat to the corresponding narrow portion; (3) a bias current source coupled to each narrow portion of the plurality of alternating narrow and wide portions; and (4) an output node adapted to output a respective current while the plurality of superconducting components is in the non-superconducting state.

Superconducting methods of determining AND, OR, AND-OR, and OR-AND logic values use single flux quantum (SFQ) pulses to assert logical inputs of a reciprocal quantum logic (RQL) gate by placing currents in input storage loops in the RQL gate and, based on the currents in the storage loops, triggering logical decision Josephson junctions (JJs) in the gate, such that an assertion or de-assertion signal corresponding to the logical function of the gate is observed at the output. The methods permit for outputs based on at least four logical inputs to be achieved.

A quantum computing devices includes: a qubit; a readout device coupled to the qubit, the readout device including a frequency filter having a filter frequency range; and an amplifier device coupled to the readout device, in which the amplifier device is configured to amplify a measurement signal from the readout device upon receiving a pump signal having a pump frequency that is outside of the filter frequency range of the frequency filter.

The various embodiments described herein include methods, devices, and systems for implementing logic gates. In one aspect, a circuit includes: (1) superconducting components; (2) heat sources, each coupled to a corresponding superconducting component and configured to selectively provide heat to that component; and (3) a current source coupled to the superconducting components and configured to selectively provide: (a) a first current to bias the components such that combination of the first current and heat from any heat source causes the components to transition to a non-superconducting state; and (b) a second current to bias the components such that (i) combination of the second current and heat from each heat source causes the components to transition to the non-superconducting state, and (ii) a combination of the second current and heat from only a subset of the heat sources does not cause the components to transition to the non-superconducting state.

A Josephson inverter gate circuit provides efficient implementation of polarity or logical inversion while eliminating the need for physically large high-efficiency magnetic transformers in the signal path. The circuit can consist of a half-twisted Josephson transmission line (JTL) or a JTL with an unshunted floating Josephson junction that produces two single flux quantum (SFQ) pulses when triggered by an SFQ input signal, which results in an output SFQ signal of reversed polarity. Implemented as a logical inverter, proper initialization of the circuit is accomplished within the signal inversion stage with flux biasing.

An on-chip Josephson parametric converter is provided. The on-chip Josephson parametric converter includes a Josephson ring modulator. The on-chip Josephson parametric converter further includes a lossless power divider, coupled to the Josephson ring modulator, having a single input port and two output ports for receiving a pump drive signal via the single input port, splitting the pump drive signal symmetrically into two signals that are equal in amplitude and phase, and outputting each of the two signals from a respective one of the two output ports. The pump drive signal excites a common mode of the on-chip Josephson parametric converter.

Superconducting circuits-based devices and methods for an A-and-not-B gate are provided. In one example, a circuit for an A-and-not-B gate including an output terminal, a first input terminal for receiving a first set of single flux quantum (SFQ) pulses, and a second input terminal for receiving a second set of SFQ pulses is provided. The circuit may further include a first stage configured to perform an exclusive-OR operation on the first set of SFQ pulses received via the first input terminal and the second set of SFQ pulses received via the second input terminal to generate an exclusive-OR result. The circuit may further include a second stage, coupled to the first stage, configured to perform an AND operation on the exclusive-OR result and the first set of SFQ pulses received via the first input terminal and provide an output via the output terminal.

A primitive race-logic temporal operator is described, comprising superconducting logic single flux quantum (SFQ) cells.

Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.