A signal divider includes: a dividing circuit arranged to generate an output oscillating signal according to a first input oscillating signal; and a signal generating circuit, coupled to the dividing circuit, for generating an injection signal to the dividing circuit. The dividing circuit is arranged to generate the output oscillating signal with a predetermined phase according to the injection signal and the first input oscillating signal.

According to a synchronization method, a basic timing signal generation circuit generates a basic timing signal. A communication control circuit generates a first communication cycle timing signal, measures an input difference between the basic timing signal and a predetermined one of first communication cycle timing signals, divides a compensation value responsive to the input difference by the number of first communication cycle timing signals, adds up a value resulting from the division in a communication cycle, compensates for timing of generating the first communication cycle timing signal with timing equal to or greater than a predetermined value, and transmits timing compensation data to external equipment. The external equipment generates a second communication cycle timing signal, compensates for timing of generating the second communication cycle timing signal based on timing of receipt of the timing compensation data, and synchronizes with the first communication cycle timing signal.

The present technology relates to a detection device and a detection method that are designed to be capable of detecting a locked state with a higher degree of accuracy.

A first edge detector detects whether there is an edge of a second clock signal in one cycle of a first clock signal. A second edge detector detects whether there is an edge of the first clock signal in one cycle of the second clock signal. The logic circuit performs a logical operation on a detection result from the first edge detector and a detection result from the second edge detector. The present technology can be applied to a circuit or the like that detects a locked state of a PLL circuit, for example.

According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.

Aspects of the disclosure are directed to multi-module frequency division. As may be implemented in accordance with one or more embodiments herein, an apparatus includes latching circuitry having three or fewer vertically-stacked transistors between power rails, which operate to provide output signals from input signals, the output signals having a frequency that is a divided representation of the frequency of the input signals. A pulse widening circuit modifies the output signals by widening a pulse thereof, providing a modified output signal. A further latching circuit may be utilized to perform a further frequency division of the modified output signal. The respective latching circuitry can be used to selectively provide frequency-divided output signals from input signals at respective divided frequencies.

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

A processing device according to an aspect of the present disclosure includes: a toggle signal reception circuit configured to receive a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and a communication circuit configured to communicate with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.