Provided is a relaxation oscillator that is very small in temperature deviation of an oscillation period. The relaxation oscillator includes an oscillation circuit, a variable frequency divider, and a counter. The oscillation circuit is configured to switch between a first clock signal having a negative value as a first-order temperature coefficient of an oscillation period, and a second clock signal having a positive value as a first-order temperature coefficient of an oscillation period, based on a signal from the counter, and to output the switched-to clock signal as a third clock signal. The variable frequency divider is configured to divide the frequency of the third clock signal that is output from the oscillation circuit, and to output the frequency-divided third clock signal as a clock signal. The counter is reset by the clock signal.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

A circuit device includes a phase comparison circuit that performs phase comparison between a reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage, a voltage controlled oscillation circuit that generates a clock signal, a dividing circuit that divides the clock signal and outputs the feedback clock signal, a processing circuit that sets a division ratio of the dividing circuit, a first register in which slope information of a waveform signal for spreading the frequency of the clock signal is set, and a second register in which amplitude information of the waveform signal is set. The processing circuit generates a waveform signal value based on the slope information and the amplitude information set in the first and second registers, and outputs division ratio data based on the waveform signal value and the division ratio setting value to the dividing circuit.

An oscillator includes a resonator, a temperature control element that controls a temperature of the resonator, a first temperature sensing element that outputs a first temperature detection signal, a second temperature sensing element that is provided at a position farther from the resonator than the first temperature sensing element and outputs a second temperature detection signal, an analog/digital conversion circuit that converts the first temperature detection signal into a first temperature code which is a digital signal, and converts the second temperature detection signal into a second temperature code which is a digital signal, and a digital signal processing circuit that generates a temperature control code for controlling the temperature control element based on the first temperature code and the second temperature code.

A temperature compensated crystal oscillator implements temperature compensation by generating and applying a temperature compensation signal via a function having a plateau region and a higher slope region, where a horizontal position of the higher slope region, a slope value in the higher slope region, and a function value change magnitude over the higher slope region are adjustable.

A circuit device includes a digital signal processor (DSP) that performs first up-sampling processing of up-sampling up-sampling target data having a first sampling frequency from the first sampling frequency to a second sampling frequency by first interpolation processing, and an arithmetic circuit that performs second up-sampling processing of up-sampling data output from the DSP from the second sampling frequency to a third sampling frequency by second interpolation processing.

The present invention relates to a crystal-free oscillator circuit (100) for channel-based high-frequency radio communication, the crystal-free oscillator circuit (100) comprising a crystal-free oscillator element (120) configured to provide a high-frequency reference signal (101), the high-frequency reference signal (101) having a frequency of at least about 1 GHz, and a phase-locked loop (PLL) circuit (110) having a feedback loop and comprising a PLL oscillator (120), wherein the phase-locked loop circuit (110) is configured to receive a high-frequency reference signal (101), to provide a feedback signal (102) in the feedback loop, and to provide a high-frequency output signal (103), the high-frequency output signal (103) being generated by the PLL oscillator (120) in response to the high-frequency reference signal (101) and to the feedback signal (102) where the feedback signal (102) is dependent on an earlier instance of the output signal (103), wherein the crystal-free oscillator circuit (100) further comprises an adjustable frequency offset circuit (210) located in the feedback loop, the adjustable frequency offset circuit (210) comprising a frequency generator (200) and being configured to offset a frequency of the feedback signal (102) in response to an adjustment control signal (104), and wherein the crystal-free oscillator circuit (100) is configured to compensate for a temperature dependency of the crystal-free oscillator circuit (100) in response to a measured current operating temperature.

A voltage controlled oscillator implements optimising its effective frequency versus voltage transfer function by generating and applying a frequency control signal via a function having a plateau region and a higher slope region, where a horizontal position of the higher slope region, a slope value in the higher slope region, and a function value change magnitude over the higher slope region are adjustable.

Provided is an oscillator including: a first resonator; a second resonator; a first oscillation circuit generating a first oscillation signal by oscillating the first resonator; a second oscillation circuit generating a second oscillation signal that has frequency-temperature characteristics different from frequency-temperature characteristics of the first oscillation signal by oscillating the second resonator; a clock signal generation circuit generating a clock signal with a frequency that is temperature compensated by temperature compensation data; and a processing circuit performing time digital conversion processing based on the first oscillation signal and the second oscillation signal, and obtaining the temperature compensation data based on measurement data of the time digital conversion processing.

Provided is an oscillator including: a first resonator; a second resonator; a first oscillation circuit generating a first oscillation signal by oscillating the first resonator; a second oscillation circuit generating a second oscillation signal that has frequency-temperature characteristics different from frequency-temperature characteristics of the first oscillation signal by oscillating the second resonator; a clock signal generation circuit generating a clock signal with a frequency that is temperature compensated by temperature compensation data; a storage unit storing information on a learned model that is machine-learned to output data corresponding to the temperature compensation data with respect to input data; and a processing circuit obtaining the temperature compensation data by performing processing based on the information on the learned model with respect to the input data based on the first oscillation signal and the second oscillation signal.