A phase locking circuit includes: a phase comparator; a pulse generation circuit; a charge pump circuit; a loop filter circuit; and a voltage-controlled oscillator. The phase comparator samples a first level in synchronization with a received reference clock, and generates a first signal to be initialized to a second level that is different from the first level by using a feedback clock. The pulse generation circuit generates a second signal in accordance with the reference clock, and controls a phase of as output signal of the voltage-controlled oscillator to be the feedback clock to have a predetermined value by inputting the first signal and the second signal as a control voltage to the voltage-controlled oscillator through the charge pump circuit and the loop filter circuit.

Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO K.sub.DCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Techniques are described herein that are capable of adjusting a center frequency of an adaptive voltage controlled oscillator (VCO) that is included in an adaptive phase lock loop (PLL) and/or a phase difference target of the adaptive PLL. An adaptive PLL is a PLL that includes an adaptive VCO. An adaptive VCO is a VCO that is capable of adjusting its center frequency and/or a phase difference target of the adaptive PLL that includes the adaptive VCO. The adaptive PLL may be configured to drive (e.g., control) a device. A drive signal that is used to drive the device and a resulting output signal that is proportional to movement of the device may be fed back to respective inputs of the adaptive PLL so that the phases of those signals may be processed to facilitate adjustment of the center frequency and/or the phase difference target.

Disclosed is a reference clock gating circuit for outputting a reliable reference clock according to an external clock. The circuit includes a detection circuit and a gating component. The detection circuit includes: a first counter counting according to triggers of the external clock and thereby generating a first clock number; a second counter counting according to triggers of an accurate slow clock and thereby generating a second clock number; and a decision circuit determining whether a ratio of the first clock number to the second clock number satisfies a predetermined condition after the second clock number reaches a predetermined number, and thereby generating a gating signal to control the gating component. If the ratio satisfies the predetermined condition, the gating component receives the external clock and outputs it as the reference clock; and if the ratio doesn't satisfy the predetermined condition, the gating component doesn't output the external clock.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and divider responsive to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal delayed relative to the bypass control signal.

A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.

TDCs for converting time periods to digital values are disclosed. An example TDC includes a ring oscillator and a residue generation circuit. Each stage of the residue generation circuit is configured to operate on outputs from two different stages of the ring oscillator. The TDC further includes a counter for counting the number of times that an output of one of the stages of the ring oscillator switches between being at a first signal level and being at a second signal level during a time period that is being converted to a digital value. The TDC also includes a combiner for generating the digital value by combining a value indicative of the number of times counted by the counter and an output of the residue generation circuit. Such a TDC may have relatively low area and low power consumption compared to the conventional TDC designs, while yielding sufficiently linear behavior.

Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

An electronic device includes a latch clock generation circuit, a command decoder, and a latency shifting circuit. The latch clock generation circuit generates a latch clock based on a chip selection signal. The command decoder generates an internal operation signal from an internal chip selection signal and an internal command generated based on the latch clock. The latency shifting circuit generates an end signal by shifting the internal operation signal in synchronization with a shifting clock by a period corresponding to a latency while an internal operation is performed.