The present invention relates to a method for preventing security breaches of a passive remote keyless entry system for authorizing access to a vehicle. The passive remote keyless entry system comprises a base station located at the vehicle and a mobile device, in particular a remote key, wherein the base station comprises a first processor unit and a first transceiver unit, the first transceiver unit comprises a timing device, the mobile device comprises a second processor unit and a second transceiver unit, an air travel time T of a single message sent back and forth from the base station to the mobile device is measured, and access to the vehicle is granted depending on the measured air travel time T.

A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.

An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal.

An exemplary system includes a PLL circuit and a precision timing circuit connected to the PLL circuit. The PLL circuit has a PLL feedback period defined by a reference clock and includes a voltage controlled oscillator configured to lock to the reference clock and having a plurality of stages configured to output a plurality of fine phase signals each having a different phase, and a feedback divider configured to be clocked by a single fine phase signal included in the plurality of fine phase signals and have a plurality of feedback divider states during the PLL feedback period. The precision timing circuit is configured to generate a timing pulse and set, based on a first combination of one of the fine phase signals and one of the feedback divider states, a temporal position of the timing pulse within the PLL feedback period.

A phase frequency detector (PFD) includes a first circuit portion and a second circuit portion. The first circuit portion receives a reference signal and activates a first error signal if the phase of the reference frequency leads the phase of a feedback signal. The second circuit portion receives the reference and activates a second error signal if the phase of the reference frequency lags the phase of the feedback signal. The first circuit portion is powered by a first power supply, and the second circuit portion is powered by a second power supply. A PLL implemented using the PFD generates a frequency output with minimized jitter.

Detection circuit for detecting electrical capacitance of electrode device in electrostatic holding device with clamp carrier, particularly for detecting component held by holding device, includes phase control circuit couplable to electrode device and has reference oscillator device, phase comparator and VCO circuit (VCOC). Phase comparator is arranged to generate a control voltage of VCOC as a function of reference signal from reference oscillator device and of VCO feedback signal from VCOC, at least one phase control circuit is configured for controlling VCOC as a function of capacitance to be detected, and for outputting an output signal characteristic of capacitance based on control voltage of VCOC, phase control circuit is configured for connection to electrode device such that VCOC contains capacitance to be detected as frequency-determining component, and reference oscillator device is configured for generating reference signal with adjustable reference frequency. Electrostatic holding device includes at least one such detection circuit.

A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.

A biological information measurement apparatus includes a phase/frequency comparison unit that outputs a deviation signal based on a phase difference between a biological signal and an oscillation signal; a loop filter; and a voltage controlled oscillation unit that generates the oscillation signal in accordance with the deviation signal that has passed through the loop filter. The apparatus further includes a CPU that estimates a SN ratio of the biological signal and analyzes a phase difference/frequency difference between the biological signal and the oscillation signal. A variable low pass filter is provided that selectively blocks a signal of a predetermined frequency band contained in the deviation signal that has passed through the loop filter and the CPU changes a cutoff frequency of the variable low pass filter based on the SN ratio and the phase difference/frequency difference.