A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

An oscillation circuit includes a first oscillation circuit that includes: a first diode that has a first negative differential resistance; a first composite inductor in which a first inductor and a second inductor are connected in series, is connected to the first diode in series; a second diode that has a second negative differential resistance and is connected to the first inductor in parallel; and a third diode that has a third negative differential resistance, is connected to the first diode in series, and is connected to the first composite inductor in parallel, wherein a burst pulse is output from a common connection point of the first inductor, the second inductor, and the second diode.

An oscillation circuit includes a first oscillation circuit that includes: a first diode that has a first negative differential resistance; a first composite inductor in which a first inductor and a second inductor are connected in series, is connected to the first diode in series; a second diode that has a second negative differential resistance and is connected to the first inductor in parallel; and a third diode that has a third negative differential resistance, is connected to the first diode in series, and is connected to the first composite inductor in parallel, wherein a burst pulse is output from a common connection point of the first inductor, the second inductor, and the second diode.

According to an exemplary embodiment of the present disclosure, a fractional-N sub-sampling phase locked loop using a phase rotator includes a frequency locked loop which is locked at a fractional-N frequency using a delta-signal modulator and a sub-sampling phase locked loop which locks a phase to a fractional multiple using a phase rotator, and the phase rotator applies a fractional multiple to a phase of a signal output from the oscillator.

According to an exemplary embodiment of the present disclosure, a fractional-N sub-sampling phase locked loop using a phase rotator includes a frequency locked loop which is locked at a fractional-N frequency using a delta-signal modulator and a sub-sampling phase locked loop which locks a phase to a fractional multiple using a phase rotator, and the phase rotator applies a fractional multiple to a phase of a signal output from the oscillator.

An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

A tracking system for a digital Phase Locked Loop (PLL), the tracking system including a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model; and a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.

A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth. The reference noise contribution and oscillator interaction suppression are thus independently controlled.

A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth. The reference noise contribution and oscillator interaction suppression are thus independently controlled.

A first phase adjuster adjusts the phase of any one of first and second AC voltages generated in a negative resistance circuit so that a shift amount Φ in a first variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the first variable phase shifter, and a second phase adjuster adjusts the phase of the other one of the first and second AC voltages generated in the negative resistance circuit so that a shift amount Φ in a second variable phase shifter falls within a range of 0 degrees≤Φ<180 degrees, and outputs the phase-adjusted AC voltage to the second variable phase shifter.