A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Embodiments of the invention may provide a phase locked loop (PLL) for a long-range and short-range frequency-modulated carrier-frequency (FMCW) RADAR system, including: a single feedback loop for generating a control signal based on differences between an output signal of the RADAR and a reference signal; a first voltage-controlled oscillator (VCO) adapted to generate a first output signal having a first loop bandwidth using the control signal; a second VCO adapted to generate a second output signal having a second loop bandwidth using the control signal; and an output switch for selecting one of the first output signal and the second output signal and outputting the selected signal as the output signal of the RADAR.

Embodiments of the invention may provide a phase locked loop (PLL) for a long-range and short-range frequency-modulated carrier-frequency (FMCW) RADAR system, including: a single feedback loop for generating a control signal based on differences between an output signal of the RADAR and a reference signal; a first voltage-controlled oscillator (VCO) adapted to generate a first output signal having a first loop bandwidth using the control signal; a second VCO adapted to generate a second output signal having a second loop bandwidth using the control signal; and an output switch for selecting one of the first output signal and the second output signal and outputting the selected signal as the output signal of the RADAR.

A master reference oscillator system is provided. The master reference oscillator system includes a plurality of reference oscillators and a hybrid matrix receiving signals from the plurality of reference oscillators and outputting a plurality of output signals having the same signal magnitude, wherein at least two output signals among the plurality of output signals may have a phase difference.

One inductive sensor is configured to maintain a fixed frequency in a resonant circuit. One apparatus includes an inductance-to-digital converter (LDC). The LDC includes a digital filter to measure an inductance change of a sensor and convert the inductance change to a digital value. The LDC further includes a digital control loop to maintain a fixed frequency in the sensor. The sensor forms an oscillator in the digital control loop. An output of the digital control loop is representative of the inductance change of the sensor.

Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.

A mobile music listening device synchronizing in a personalized way music and movement, and dedicated to improving the kinematics of the runner. Thanks to inertial units connected to a smartphone, the runner's steps are detected in real time by the mobile application. A dedicated algorithm adapts the pulsation of the musical excerpts in such a way as to bring the runner to a suitable cadence, capable of preventing injuries. A method for the synchronization of the rhythmic stimulation with the biological variability using a Kuramoto model characterized in that phase oscillator with a coupling term from the movement dynamics with parameters of, coupling strength, maximum and minimum frequencies for a fraction of the unmodified song frequency, maximum difference between the tempo and target frequency, Target the target frequency.

A mobile music listening device synchronizing in a personalized way music and movement, and dedicated to improving the kinematics of the runner. Thanks to inertial units connected to a smartphone, the runner's steps are detected in real time by the mobile application. A dedicated algorithm adapts the pulsation of the musical excerpts in such a way as to bring the runner to a suitable cadence, capable of preventing injuries. A method for the synchronization of the rhythmic stimulation with the biological variability using a Kuramoto model characterized in that phase oscillator with a coupling term from the movement dynamics with parameters of, coupling strength, maximum and minimum frequencies for a fraction of the unmodified song frequency, maximum difference between the tempo and target frequency, Target the target frequency.

Apparatus and methods of automatically trimming a PCB-based LC circuit. The apparatus may comprise an interface to a printed circuit board (PCB). The PCB may include a PCB inductor and a PCB capacitor to form an LC circuit. The LC circuit may have an LC circuit frequency. The apparatus may comprise a variable capacitor communicatively coupled to the interface and configured to adjust an effective capacitance of the LC circuit.

A signal generation circuit includes: a clock circuit configured to receive a flag signal and generate a clock signal; a control circuit configured to generate a control circuit; and a generation circuit connected to both the clock circuit and control circuit and configured to receive the clock signal, the control signal, and the flag signal and generate a target signal, wherein when the flag signal changes from a first level to a second level, the target signal changes from a third level to a fourth level, and after the target signal is maintained at the fourth level for a target duration, the target signal changes from the fourth level to the third level; and the generation circuit is further configured to determine the target duration according to the clock signal and control signal.