An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.

An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

An oscillator-based sensor interface circuit includes first and second input nodes arranged to receive first and second electrical signals representative of an electrical quantity, respectively; an analog filter; a first oscillator arranged to receive a first oscillator input signal and a second oscillator different from the first oscillator and arranged to receive a second oscillator input signal; a comparator arranged to compare signals coming from the first and second oscillators; a first feedback element arranged to receive a representation of the digital comparator output signal and to convert the representation into a first feedback signal to be applied to the oscillation means; a digital filter arranged to yield an output signal, being an filtered version of the digital comparator output signal; a second feedback element arranged to receive the output signal and to convert the output signal into a second feedback signal.

A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.

An analog-to-digital convertor of an integration type, includes: a charging circuit having a capacitor configured to store electric charges based on an input current; a discharging circuit configured to discharge the electric charges stored in the capacitor; and a counting circuit configured to count a charge-discharge count of the capacitor in a first conversion period and in a second conversion period, in order to convert a current value of the input current into a digital value, wherein the first conversion period includes a first pre-charging period and a first counting period, the second conversion period includes a second pre-charging period and a second counting period, and the analog-to-digital convertor further comprises a phase changing circuit configured to change a first phase of an output signal of the charging circuit in the first counting period to a second phase in the second counting period.

An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.

An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.

A temperature stabilization technique for a digital-to-analog converter (DAC). The DAC is kept operating while a load, for example an analog computer, is disconnected from the DAC in order to reduce temperature changes that otherwise occur when the DAC is idle. The DAC may be supplied with adjusted input to compensate for changes in dissipation caused by the removal of the load.

An analog-to-digital converter, ADC, circuitry, comprises: an integrator connected to a capacitor, the integrator being configured to switch between integrating an analog input signal for ramping an integrator output and integrating a reference input signal for returning integrator output towards a threshold; a comparator for comparing integrator output to the threshold; and a timer for determining a time duration during which the reference input signal is integrated, the time duration providing a digital representation of an analog input signal value; the ADC circuitry further comprising a feedforward noise shaping loop configured to store a quantization error signal based on digitizing a first sample, the comparator being configured to receive a feedforward noise shaping signal for changing the threshold for digitizing a later sample of the analog input signal following the first sample.