The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started.

An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the i.sup.th pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.

In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

A temperature-to-digital converter includes a temperature sensor circuit, an analog-to-digital converter (ADC), and a digital processing circuit. The temperature sensor circuit is configured to generate first and second complementary-to-absolute-temperature (CTAT) voltages based on a sensed absolute temperature. The ADC is configured to receive the first and second CTAT voltages. Further, during first and second conversion cycles of the ADC, the ADC is configured to receive the first and second CTAT voltages, and generate first and second digital voltages, respectively. The first and second digital voltages are generated based on the first and second CTAT voltages, respectively, and a difference between the first and second CTAT voltages. The digital processing circuit is configured to generate, based on the first and second digital voltages, a temperature output voltage that is independent of a gain of the ADC and a digital representation of the absolute temperature.

In one embodiment, a waveform generating device includes a first DA converter converting input data, a controller outputting a first signal having a command value based on the input data, and a second signal having a command value differing by a constant value from the first signal, a second DA converter converting the first signal, a third DA converter converting the second signal, and a combiner combining the output of the first DA converter, the output of the second DA converter, and the output of the third DA converter. When a value of a predetermined first high-order bit of the input data is inverted, the controller changes the command value of the first signal such that a value of the first high-order bit or a second high-order bit different from the first high-order bit is inverted.

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold.

The present invention relates to an incremental analog to digital converter incorporating noise shaping and residual error quantization. In one embodiment, a circuit includes an incremental analog to digital converter, comprising a loop filter that filters an analog input signal in response to receiving a reset signal, resulting in a filtered analog input signal, and a successive approximation register (SAR) quantizer, coupled with the filtered analog input signal, that converts the filtered analog input signal to an intermediate digitized output of a first resolution based on a reference voltage, wherein the SAR quantizer comprises a feedback loop that shapes quantization noise generated by the SAR quantizer as a result of converting the filtered analog input signal; and a digital filter, coupled with the intermediate digitized output, that generates a digitized output signal of a second resolution, greater than the first resolution, by digitally filtering the intermediate digitized output.

A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

The value range for which an error in a digital signal can be corrected is expanded. A control unit generates characteristic information indicating the relationship between an input and an output of an A/D converter and sets a value range. The control unit, in a case in which a value indicated by a first digital signal obtained by the A/D converter converting a first analog voltage signal is within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of the first digital signal and characteristic information, and in a case in which a value indicated by the first digital signal is not within the value range, A/D converts the first analog voltage signal and generates corrected digital information on the basis of a second digital signal obtained by the A/D converter converting the second analog voltage signal and characteristic information.

A semiconductor device comprising: a voltage generator configured to generate a voltage; a first analog-to-digital (AD) converter configured to convert an analog value based on a voltage generated by the voltage generator into a first digital value; and a second AD converter configured to convert an analog value based on a voltage generated by the voltage generator into a second digital value, wherein the voltage generator generates voltages by dividing a power supply voltage by resistive elements.