Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.

Techniques are described that can be used to extract an offset and a gain of a signal chain, which can be used for digital correction of an analog-to-digital converter (ADC) output to help achieve a life time and temperature stable ADC output. For example, using various techniques, a value for a voltage reference VREF and a value for ground (GND) (or other reference voltage) can be converted, which can then be used to determine gain and offset, respectively, of the signal chain.

An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.

Embodiments are provided for a method of operating a receiver system, the receiver system comprising one or more channels, the method comprising: monitoring a residual DC (direct current) offset in a present channel by sampling an output of an analog-to-digital converter (ADC) of the present channel; adjusting a DCO (direct current offset) correction signal that corresponds to the residual DC offset in response to an absolute value of the residual DC offset exceeding a programmable DCO threshold; and subtracting the DCO correction signal from an analog signal provided to the ADC to reduce the residual DC offset below the programmable DCO threshold.

A method of processing an analog signal includes receiving, into signal processing circuitry from compensation circuitry, an offset compensation signal, the offset compensation signal having (i) a polarity opposite a polarity of a gain error of the signal processing circuitry and (ii) a magnitude equal to a nominal compensation value plus a deviation. The method includes generating, by the signal processing circuitry, an output signal based on an analog signal received into the signal processing circuitry, including applying the offset compensation signal to an intermediate signal generated by the signal processing circuitry. The method includes scaling the output signal based on the deviation between the magnitude of the offset compensation signal and the nominal compensation value.

Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry, comprising a pair of latch input transistors which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry; and gain-stage circuitry, comprising a pair of cross-coupled gain-stage output transistors connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.

An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.

A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.