A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimation correction.

An A/D converter includes: an input unit configured to receive an analog input signal, a preprocessing unit configured to convert the input signal into a digital preprocessing signal based on a dynamic range of the input signal and a first resolution corresponding to a predetermined first bit number, a first conversion unit configured to convert the preprocessing signal into a first output signal based on a second resolution corresponding to a second bit number smaller than the first bit number, and a second conversion unit configured to convert the preprocessing signal into a second output signal based on a third resolution corresponding to a third bit number which is smaller than the first bit number and is different from the second bit number.

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each input line to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V.sub.ADC.sub._.sub.fs/128+V.sub.ADC.sub._.sub.fs/256+V.sub.ADC.sub._.sub.fs/512+V.sub.ADC.sub._.sub.fs/1024 when m equals 4 and where V.sub.ADC.sub._.sub.fs is the full-scale voltage of the ADC.

An A/D converter includes: an input unit configured to receive an analog input signal, a preprocessing unit configured to convert the input signal into a digital preprocessing signal based on a dynamic range of the input signal and a first resolution corresponding to a predetermined first bit number, a first conversion unit configured to convert the preprocessing signal into a first output signal based on a second resolution corresponding to a second bit number smaller than the first bit number, and a second conversion unit configured to convert the preprocessing signal into a second output signal based on a third resolution corresponding to a third bit number which is smaller than the first bit number and is different from the second bit number.

Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

In an analog-to-digital converter, primary latches respectively latch an output of a corresponding one of delay units at respective sample times of different first clocks. The primary latches include at least first and second primary latches, and secondary latches include at least first and second secondary latches respectively corresponding to the at least first and second primary latches. Each of the at least first and second secondary latches is configured to latch, at a sample time of a common second clock, an output of a corresponding one of the at least first and second primary latches. The common second clock is based on at least one of the first clocks.

This application relates to circuitry for processing sense signals generated by MEMS capacitive transducers for compensating for distortion in such sense signals. The circuitry has a signal path between an input (204) for receiving the sense signal and an output (205) for outputting an output signal based on said sense signal. Compensation circuitry (206, 207) is configured to monitor the signal at a first point along the signal path and generate a correction signal (Scorr); and modify the signal at at least a second point along said signal path based on said correction signal. The correction signal is generated as a function of the value of the signal at the first point along the signal path so as to introduce compensation components into the output signal that compensate for distortion components in the sense signal. The first point in the signal path may be before or after the second point in the signal path. The monitoring may be performed in an analogue or a digital part of the signal path and in either case the modification may be applied in an analogue or a digital part of the signal path.

When a level of a signal output from a pixel is higher than a comparison level, the signal output from the pixel is converted into a digital signal during a first period by using a first reference signal. If the level of the signal output from the pixel is lower than the comparison level, the signal output from the pixel is converted into a digital signal during a second period that is longer than the first period by using a second reference signal.

An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

Methods and systems for an analog-to-digital converter with near-constant common mode voltage may comprise, in an analog-to-digital converter (ADC) having sampling switches on each of two input lines to the ADC, N double-sided and M single-sided switched capacitors on each input line: sampling an input voltage by closing the sampling switches, opening the sampling switches and comparing voltage levels between the input lines, iteratively switching the double-sided switched capacitors between a reference voltage (Vref) and ground, and iteratively switching the single-sided switched capacitors between ground and voltages that may equal Vref/2.sup.x where x ranges from 0 to m1 and m is a number of single-sided switched capacitors per input line. A common mode offset of the ADC may be less than V.sub.ADC.sub._.sub.fs/128+V.sub.ADC.sub._.sub.fs/256+V.sub.ADC.sub._.sub.fs/512+V.sub.ADC.sub._.sub.fs/1024 when m equals 4 and where V.sub.ADC.sub._.sub.fs is the full-scale voltage of the ADC.