The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include performing a single-point Fast Fourier Transform (FFT) (or complex downconversion with DC average) for a number of samples to obtain a transform for each of the number of samples, phase aligning a set of phases associated with each transform, and averaging each transform to generate an analog-to-digital converter (ADC) power value. Further, the disclosed embodiments may include generating a compensation value based on the analog-to-digital converter power value and applying the compensation value to the calibration circuit of the mixer to compensate for a second-order intermodulation product.

An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

A digitizing circuit includes a port connectable to a device under test (DUT), an integrating analog-to-digital converter (ADC), a high-speed ADC, one or more processors to apply a digital filter to output samples of the high-speed ADC to produce filtered samples, find differences between the filtered samples and samples from the integrating ADC to produce error values, and add the error values to the output samples of the high-speed ADC. A method of producing a digital signal includes receiving an input analog signal at an integrating analog-to-digital converter (ADC) and a high-speed ADC, applying a digital filter to output samples of the high-speed ADC to produce filtered samples, the digital filter matched to timing and filtering of the integrating ADC, finding differences between the filtered samples to output samples of the integrating ADC to produce error values, and adding the error values to the output samples of the high-speed ADC.