Many electronic circuits rely on the ratio of one component to other components being well defined. Current flow in component can warm the component causing its electrical properties to change, for example the resistance of a resistor may increase due to self-heating as a result of current flow. The present disclosure provides a way to reduce temperature variation between components so as to reduce electrical mismatch between them or the consequences of such mismatch. This is important as even a change of resistance of, for example, 20-50 ppm in a resistor can result in non-linearity exceeding the least significant bit value of a 16 bit digital to analog converter.

A method and apparatus for decomposition of signals with varying envelope into offset components are disclosed here, that sample the time variant envelope of a single carrier (SC) or a multi-carrier (MC) band limited signal, quantizes the sampled value using N.sub.b quantization bits and decomposes the sample into N.sub.b in-phase and quadrature components that are combined in pairs and modulated to generate a set of N.sub.b offset signals. The pulse shape applied in each offset signal is selected according to the spectral mask needed for the signal and to minimize envelope fluctuations in each offset signal from the set of N.sub.b components.

Systems and techniques relating to a digital-to-analog converter (DAC) are described. A described DAC cell includes a differential switch pair coupled with a cross-coupled switch pair. Gate terminals of the differential switch pair are arranged to respectively receive an input signal to the cell and an inverted version of the input signal to respectively drive the gate terminals of the differential switch pair. Gate terminals of the cross-coupled switch pair are arranged to respectively receive the input signal and the inverted version of the input signal to respectively drive the gate terminals of the cross-coupled switch pair. The cross-coupled switch pair is configured to reduce or eliminate net differential transient current between switch output terminals of the differential switch pair. A current-to-voltage converter coupled with the switch output terminals of the differential switch pair generates a voltage that forms at least a portion of an output of the digital-to-analog converter.

A method may include processing an analog input signal with a first processing path configured to generate a first digital signal based on the analog input signal; processing the analog input signal with a second processing path configured to generate a second digital signal based on the analog input signal, and adapting a response of an adaptive filter configured to generate a filtered digital signal from the second digital signal to reduce a difference between the filtered digital signal and the first digital signal. The method may additionally or alternatively include determining nonlinearities present in the second processing path based on comparison of the first digital signal and the second digital signal, and applying a linear correction to the second digital signal to generate a corrected second digital signal with decreased nonlinearity from that of the second digital signal.

A method may include processing an analog input signal to generate a first digital signal in accordance with a first analog gain, processing the analog input signal to generate a second digital signal in accordance with a second analog gain, and generating a digital output signal of the processing system from one or both of the first digital signal and the second digital signal based on a magnitude of the analog input signal and setting the first analog gain based on the magnitude of the analog input when the digital output signal is generated from the second digital signal.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.

Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.

An analog to digital converter temperature compensation system comprising a comparator configured to compare an analog input signal to a compensated feedback signal and generate a comparator output. A SAR module processes the comparator output to generate a digital signal. A digital to analog converter, biased by a biasing signal having temperature change induced error, is configured to convert the digital signal to a feedback signal and a detector is configured to detect a signal that is proportional to temperature. A look-up table is configured to receive and convert the signal that is proportional to temperature to a compensation signal such that the compensation signal compensates for the temperature change induced error in the biasing signal. A summing node combines the feedback signal with the compensation signal to create a compensated feedback signal.

Disclosed are an analog-to-digital conversion circuit, an analog-to-digital conversion device, and a digital x-ray imaging system. The analog-to-digital conversion circuit includes a first reference voltage source, a second reference voltage source, a first analog-to-digital converter connected to the first reference voltage source, a second analog-to-digital converter connected to the second reference voltage source, a connecting circuit connected to the first analog-to-digital converter and the second analog-to-digital converter, respectively, and a current source having negative temperature coefficient configured to be connected to the first reference voltage source and the second reference voltage source, respectively.

A solid-state image sensor includes: an input transistor configured to output, from a drain, a drain voltage according to an input voltage input to a source in a case where the input voltage substantially coincides with a predetermined reference voltage input to a gate; and an output transistor configured to output a signal indicating whether or not a difference between the input voltage input to a source and the drain voltage input to a gate exceeds a predetermined threshold voltage as a comparison result between the input voltage and the reference voltage.