A method and apparatus for decomposition of signals with varying envelope into offset components are disclosed here, that sample the time variant envelope of a single carrier (SC) or a multi-carrier (MC) band limited signal, quantizes the sampled value using N.sub.b quantization bits and decomposes the sample into N.sub.b in-phase and quadrature components that are combined in pairs and modulated to generate a set of N.sub.b offset signals. The pulse shape applied in each offset signal is selected according to the spectral mask needed for the signal and to minimize envelope fluctuations in each offset signal from the set of N.sub.b components.

A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).

An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to output a first digital value corresponding to an analog input voltage. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values into a digital output voltage.

A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency.

Methods and systems for performing analog-to-digital conversion is provided. In one example, an analog-to-digital converter (ADC) circuit comprises a leakage compensation circuit and a quantizer. The leakage compensation circuit is configured to: receive an input signal, the input signal being susceptible to a drift due to a charge leakage; receive a reference signal; and generate a leakage-compensated signal pair to compensate for the charge leakage, wherein the leakage-compensated signal pair comprises one of: (a) a leakage-compensated version of the input signal and the reference signal, (b) the input signal and a leakage-compensated version of the reference signal, or (c) a leakage-compensated version of the input signal and a leakage-compensated version of the reference signal. The quantizer is configured to perform a leakage-compensated quantization of the input signal based on the leakage-compensated signal pair to generate a digital output representing the input signal.

A time-interleaved SAR-ADC employs calibrated SAR-ADC circuits to convert sampled voltage levels into serial digital data. Variable delay clock circuits synchronize clock signals received at the respective SAR-ADCs to sampling points of analog serial data. IC and environmental fluctuations cause delay in the variable delay clock circuits to skew the clock signals. A calibrated SAR-ADC detects changes to the delays in the variable delay clock circuits. By delaying a first clock signal in the variable delay clock circuit, and comparing a phase of the delayed clock signal to a phase-shifted clock signal having a known phase shift relative to the first clock signal, a change in the delay of the variable delay clock circuit can be detected as a phase difference. Based on an indication of a phase difference, a delay control signal is generated to control the delay in the variable delay clock.

A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

A field measuring device includes a sensor, a measuring transducer, and interface electronics. The interface electronics include a measuring and control device, and first and second terminals for connecting an external electrical device. A current controller and a current measuring device are connected in series in a terminal current path between the first and second terminals. The interface electronics has a voltage source that can be switched on in the terminal current path and disconnected from the terminal current path, so that the voltage source can drive a current in the terminal current path in the switched-on state and in the case of a connected external electrical device. The measuring and control device actuates and reads the current controller, the current measuring device, and the voltage source such that a current signal is output or input via the first and second terminals when an external device is connected.

Various embodiments of a segmented R-DAC are disclosed. In one embodiment, a segmented R-DAC includes first and second DACs arranged to receive most and least significant bits, respectively. The segmented R-DAC also includes a first capacitor coupled between an output of the first DAC and an output of the second DAC, and a second capacitor coupled between the output of the second DAC and a ground node. The capacitance of the second capacitor has a value that is a predetermined multiple of the capacitance value of the first capacitor.