The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.

The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.

An apparatus and method for carrier frequency estimation include a carrier frequency estimator having: a frequency input terminal disposed to receive a frequency-domain input signal comprising a plurality of symbols; a plurality of candidate pipelines, each comprising a frequency adder coupled to the frequency input terminal, a bit converter coupled to the frequency adder, a multi-bit buffer coupled to the bit converter; and a correlator coupled to the multi-bit buffer, respectively; and a candidate pipeline selector coupled to the correlators.

A device for converting a digital input signal into an analog output signal is provided. The device includes a first digital to analog converter configured to generate a first analog signal, and a second digital to analog converter configured to generate a second analog signal. The device further includes a signal splitter configured to couple out a feedback signal from the second analog signal. The device further includes a first signal combiner configured to subtract the feedback signal from the first analog signal to generate an error signal. The device further includes an amplifier configured to amplify the error signal, resulting in an amplified error signal. The device further includes a second signal combiner configured to combine the amplified error signal and a signal derived from the second analog signal, resulting in the analog output signal.

A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles. Each successive approximation cycle of the plurality of successive approximation cycles including: generating a DAC input word using a successive approximation register (SAR), offsetting the DAC input word to form an offset DAC input word when the successive approximation cycle corresponds to the at least one sub-binary weighted reference element, applying the offset DAC input word to an input of the DAC to produce a first DAC output signal, comparing the first DAC output signal with the sampled input signal using a comparator, and setting a bit of the SAR based on the comparison.

A TI ADC circuit (30) comprises a plurality of L analog inputs (32-1, 32-2, 32-3) and a plurality of L digital outputs (34-1, 34-2, 34-3). The i:th analog input (32-i) is for receiving an i:th analog input signal. The i:th digital output (34-i) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit (30) comprises a set (90) of sub ADCs (100-1100-K). The TI ADC circuit (30) is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (100-1100-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer >1. The number K of sub ADCs in the set (90) of sub ADCs (100-1100-K) exceeds L.Math.M. TI ADC circuit (30) comprises a control circuit (120) configured to select, for each input sample of each of the L analog input signals, which available sub ADC (100-1100-K) in the set (90) of sub ADCs that should operate on that input sample, such that at least some of the sub ADCs (100-1100-K), over time, operate on input samples of each of the L analog input signals.

A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.

Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and/or calibration based on signal measurements taken at the output stage of a device comprising the DAC.

Embodiments disclosed herein may reduce or even eliminate spurs introduced into the signals during analog to digital or digital to analog conversions. The spurs may be introduced by components such as clocks of the converter circuits. In an analog to digital conversion, the input signal may be split into two parts: the first portion passing through a first analog to digital converter (ADC) and an inverted second portion passing through a second ADC. A digital subtractor may subtract the output of the second ADC from the output of the first ADC converter thereby reducing the spurs. In digital to analog conversion, a digital input is passed through a first digital to analog converter (DAC) and an inverted digital input is passed through a second DAC. The output of the second DAC is inverted and combined with the output of the first DAC to reduce the spurs.