A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.

A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input

A TI ADC circuit (30) comprises a plurality of L analog inputs (32-1, 32-2, 32-3) and a plurality of L digital outputs (34-1, 34-2, 34-3). The i:th analog input (32-i) is for receiving an i:th analog input signal. The i:th digital output (34-i) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit (30) comprises a set (90) of sub ADCs (100-1-100-K). The TI ADC circuit (30) is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (100-1-100-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer >1. The number K of sub ADCs in the set (90) of sub ADCs (100-1-100-K) exceeds L.Math.M. TI ADC circuit (30) comprises a control circuit (120) configured to select, for each input sample of each of the L analog input signals, which available sub ADC (100-1100-K) in the set (90) of sub ADCs that should operate on that input sample, such that at least some of the sub ADCs (100-1-100-K), over time, operate on input samples of each of the L analog input signals.

A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal V.sub.in, a sample-and-hold stage which receives V.sub.in and outputs sampled signal V.sub.in,samp, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, V.sub.in,samp is compared with a threshold voltage V.sub.thresh, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to V.sub.in,samp. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to V.sub.in,samp.

A device for converting a digital input signal into an analog output signal is provided. The device includes a first digital to analog converter configured to generate a first analog signal, and a second digital to analog converter configured to generate a second analog signal. The device further includes a signal splitter configured to couple out a feedback signal from the second analog signal. The device further includes a first signal combiner configured to subtract the feedback signal from the first analog signal to generate an error signal. The device further includes an amplifier configured to amplify the error signal, resulting in an amplified error signal. The device further includes a second signal combiner configured to combine the amplified error signal and a signal derived from the second analog signal, resulting in the analog output signal.

A successive approximation register A/D converter (SARADC) has redundancy. An analog unit samples an analog input voltage and generates a comparison signal indicating a magnitude relationship between a threshold voltage corresponding to a control code and the analog input voltage. A logic unit generates, in an i-th (i?1) cycle, a first value obtained by adding a weight of an (i+1)-th cycle to a control code of the i-th cycle and a second value obtained by subtracting the weight of the (i+1)-th cycle from the control code of the i-th cycle. When a comparison signal of the cycle is determined, the logic unit supplies one of the first value and the second value corresponding to the comparison signal to the analog unit 110 as a control code of the (i+1)-th cycle.

A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN), detecting if a binary code determined from the analog input signal (V.sub.IN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*.sub.RES) and a calibration bit (B*.sub.LSB), analyzing a least significant bit of the digital signal (C.sub.OUT) and the calibration bit (B*.sub.LSB), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*.sub.LSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Systems, methods, and circuitries for converting an analog voltage to a digital signal are provided. In one example a method to convert an analog voltage into a binary sequence that represents the voltage includes two modes. In the first mode, in each cycle, values for a next two or more of consecutive most significant bits (MSBs) in the sequence are determined using M comparators, wherein M is equal to or greater than 3. In a second mode, in each cycle, M redundant comparison results are determined using the M comparators. A value for the LSB is determined based on the M redundant values. At an end of conversion, the sequence of N bit values is generated based on the MSBs and the LSB.