This application discloses a temperature feedback control apparatus, method. The method includes two electric switches, a feedback control unit and an optical component. A first electric switch is configured to control that only a first channel of at least two channels that correspond to the first electric switch is conducted at a moment, to feed back an optical signal of a target optical component connected to the first channel to the feedback control unit. The feedback control unit is configured to calculate temperature of the corresponding optical component based on an electrical signal converted from the optical signal, to obtain a control signal. The second electric switch is configured to control, when the first channel is conducted, that only the second channel is conducted, to transmit the control signal to the target optical component to adjust its temperature. The optical component connects to both the first and second channels.

A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.

A controller for a power converter device, wherein the controller is configured to provide for switching of a switching component of the power converter device based on a feature in a control signal, sample at least one parameter of the power converter device upon expiry of a predetermined time period after switching of the switching component; and output the sample of the at least one parameter.

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.

A real-time digital sparkle filter for processing high-speed analog to digital converter (ADC) data is disclosed. The real-time digital sparkle filter for processing a continuous stream of digital data, comprising a high-speed data interface, a digital sparkle filter, and a buffer sequencer. The high-speed data interface receives sample data from an analog to digital converter (ADC). The digital sparkle filter operates continuously on the sample data without losing any samples. The digital sparkle filter comprises one or more logic implemented using field-programmable gate arrays (FPGAs) configured to continuously process the data without degrading the signal content. The buffer sequencer comprises an input buffer and an output buffer. The input buffer receives the digital data stream data using a first in first out buffer mechanism. The output buffer receives the processed output of the sparkle filter, thereby eliminating the sparkle noise without degrading data content.

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

Digital to analog converter generates an analog output corresponding to a digital input by controlling DAC cells using bits of the digital input. The DAC cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the DAC cells may have duty cycle error or mismatches. To compensate for the duty cycle error of a DAC cell, a small amount of charge is injected into a low-impedance node of a DAC cell when the data signal driving the DAC cell transitions, or changes state. The small amount of charge is generated using a capacitive T-network, and the polarity of the charge injected is opposite of the error charge caused by duty cycle error. The opposite amount of charge thus compensates or cancels out the duty cycle error, and duty cycle error present at the output of the DAC cell is reduced.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.