A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

A duty cycled voltage reference circuit is turned on and off synchronously with the operation of a second, reference-consuming, duty-cycled circuit to which it supplies a reference. When the reference consuming circuit no longer has need of the reference, the voltage reference circuit itself is then also powered down. The reference circuit is then powered back up for the next duty cycle sufficiently in advance of the reference consuming circuit such that any auto-zeroing and noise filtering operations required by the reference circuit are complete and a stable reference voltage is output at least simultaneously with, or slightly before, the reference consuming circuit begins to make use of the voltage reference signal. In this manner, synchronous duty-cycled operation of the voltage reference circuit with the reference-consuming circuit is obtained, with the consequence that power consumption by the reference circuit is reduced.

A signal processing circuit includes a clock generating circuit, a divider circuit, a converter, and an amplifier. The clock generating circuit outputs a first clock. The divider circuit divides the first clock to output a second clock having a frequency lower than a frequency of the first clock. The converter converts an input signal into a digital signal based on a first clock output from the clock generating circuit and a second clock output from the divider circuit. The amplifier, disposed between the clock generating circuit and the divider circuit, has a phase variation property opposite to a phase variation property of the divider circuit. The phase variation property of the divider circuit indicates a relationship between a phase variation amount of an output signal with respect to an input signal in the divider circuit and an ambient temperature of the divider circuit.

A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

This description relates generally to piecewise temperature compensation. In an example, a circuit includes a knee code selector that can be configured to set a knee point temperature for a correction current responsive to a respective knee point temperature code of knee point temperature codes and a respective temperature sense signal of temperature sense signals. The circuit includes an output circuit that can be configured to provide the correction current responsive to the respective temperature sense signal and temperature voltages, and a trim digital to analog converter (DAC) that can be configured to provide a piecewise compensation current responsive to the correction current and a respective trim code of trim codes.

An AD conversion apparatus includes an AD conversion unit; a reference voltage switching unit that is disposed between an output of a sensor and an analog input terminal of the AD conversion unit and is connectable to the output of the sensor and a plurality of reference voltage lines; and a control unit to control switching the reference voltage input to the AD conversion unit by connecting the reference voltage switching unit to one of the reference voltage lines and to the output of the sensor. An analog output value of the sensor is input to the analog input terminal of the AD conversion unit via the reference voltage switching unit and is converted into a digital value.

An inertial force sensor includes: an acceleration detection element; a temperature sensor that detects an ambient temperature of the acceleration detection element; a bridge circuit that processes an output signal from the acceleration detection element; an AD converter that converts an analog signal output from the bridge circuit into a digital signal, and outputs the digital signal; a calculation circuit that performs calculation on the output signal from the AD converter; and a storage that stores correction data for correcting a variation in the output signal from the AD converter due to a temperature change. The correction data are coefficients of a formula expressed by a calibration curve that is a quadratic or higher-degree curve, and the storage stores, as the correction data, the coefficients of the calibration curve of each of a plurality of patterns that differ between a predetermined temperature or more and less than the predetermined temperature.

A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

A signal processing circuit includes a clock generating circuit, a divider circuit, a converter, and an amplifier. The clock generating circuit outputs a first clock. The divider circuit divides the first clock to output a second clock having a frequency lower than a frequency of the first clock. The converter converts an input signal into a digital signal based on a first clock output from the clock generating circuit and a second clock output from the divider circuit. The amplifier, disposed between the clock generating circuit and the divider circuit, has a phase variation property opposite to a phase variation property of the divider circuit. The phase variation property of the divider circuit indicates a relationship between a phase variation amount of an output signal with respect to an input signal in the divider circuit and an ambient temperature of the divider circuit.

A sensing radar includes a transmitter configured to transmit bursts of pulses, a receiver configured to receive a signal comprising an echo from the bursts of pulses and a leakage of the bursts of pulses from the transmitter to the receiver; an analog-to-digital converter (ADC) coupled to the receiver, and a processor coupled to the ADC. At least one of thresholds of the ADC is configured such that the ADC has a chance of at least 5% to be tripped by thermal noise at an input of the ADC regardless of an amplitude of the signal. The processor is configured to process an output of the ADC at intervals of the bursts of pulses and ignore durations of transmitting the bursts of pulses to retrieve the echo from the signal.