Disclosed are a method and a device for improving an output accuracy of a digital-to-analog converter. The method includes: calculating an output error of the digital-to-analog converter based on output accuracy and an input error of the digital-to-analog converter; obtaining at least one of the output error, comparing the at least one output error against a preset threshold, and adjusting an integer input value of the digital-to-analog converter according to a comparison result.

Various background calibration techniques to calibrate inter-stage gain, e.g., in pipelined ADCs, are described to allow open loop amplifier circuits to be used as residue amplifiers for better power efficiency. Using various techniques, a well-controlled perturbation can be injected between two conversions and the actual perturbation after a residue amplifier can be measured. By comparing the actual measurement against an expected value, the gain information of the residue amplifier can be estimated and then calibration can be applied.

A digital-to-analog converter (DAC) device includes a DAC circuitry, a calibration circuitry, and a randomization circuitry. The DAC circuitry includes a first DAC circuit and a second DAC circuit. The first DAC circuit is configured to generate a first signal according to least significant bits of an input signal. The second DAC circuit is configured to output a second signal. The calibration circuitry is configured to compare the first signal with the second signal, in order to calibrate the second DAC circuit. The randomization circuitry is configured to randomize most significant bits of the input signal, in order to generate first control signals, in which the second DAC circuit is further configured to generate the second signal according to the most significant bits or the first control signals.

An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number n. The adder circuit includes sets of scaled capacitors, each capacitor connected to an n.sup.th input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2.sup.(n)*a unit capacitance (C.sub.UNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance.

The disclosure provides a circuit. The circuit includes a zone detection block that generates a control signal in response to an input signal. An amplifier generates an amplified signal in response to the input signal and the control signal. An analog to digital converter (ADC) is coupled to the amplifier and samples the amplified signal to generate a digital signal. A digital corrector is coupled to the zone detection block and the ADC, and transforms the digital signal to generate a rectified signal based on the control signal and an error signal. An error estimator is coupled to the zone detection block and receives the rectified signal as a feedback. The error estimator generates the error signal in response to the control signal and the rectified signal.

A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number n. The adder circuit includes sets of scaled capacitors, each capacitor connected to an n.sup.th input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2.sup.(n)*a unit capacitance (C.sub.UNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.