Novel solutions for calibration of a digital-to-analog converter (DAC). Some solutions allow for the calibration of a DAC without an isolation switch and/or calibration based on signal measurements taken at the output stage of a device comprising the DAC.

A method for improving performance of a superconducting, flux-quantizing analog to digital converter (SFADC), comprising the following steps. The first step involves providing a known digitally-modulated signal as an input to the SFADC. Another step provides for generating an output with the SFADC based on the known digitally-modulated signal. Another step provides for comparing the characteristics of the output with ideal characteristics to identify an individual rapid single flux quantum (RSFQ) element of the SFADC that is contributing one or more of noise and error to the output. Another step provides for altering one or more of a bias, a delay, and a temperature of the individual RSFQ element to reduce one or more of the noise and the error.

An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

An oscillator-based sensor interface circuit comprises at least two oscillators, at least one of which is arranged for receiving an electrical signal representative of an electrical quantity being a converted physical quantity, phase detection means arranged to compare output signals of the at least two oscillators and for outputting a digital phase detection output signal in accordance with the outcome of the comparing, a feedback element arranged for converting a representation of the digital phase detection output signal into a feedback signal used directly or indirectly to maintain a given relation between oscillator frequencies of the at least two oscillators, detection means for detecting a difference between the at least two oscillators; and at least one tuning element arranged for receiving the detected difference and for tuning at least one characteristic of the oscillator-based sensor interface circuit.

A time-interleaved analog to digital converter (ADC) circuit includes an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal, a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude, and an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals. A time-interleaved ADC has an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal. A digital output subtractor module is configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.

A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.

Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.