A semiconductor device is provided that includes an amplification circuit, a downstream circuit, and a clipping circuit. The amplification circuit includes a sampling capacitor, a feedback capacitor, and an operational amplifier circuit. The sampling capacitor holds air input signal on which sampling is performed, as a signal whose reference is a first reference voltage. The signal that is held in the sampling capacitor is transferred to the feedback capacitor. The operational amplifier circuit amplifies the signal that is held in the sampling capacitor, according to a ratio between values of the sampling capacitor and the feedback capacitor, and outputs the amplified signal, as a signal whose reference is a second reference voltage. The clipping circuit limits a voltage of an output signal of the operational amplifier circuit to a predetermined voltage or below.

Embodiments of the disclosure relate to an analog-to-digital converter (ADC) with gain adjustment. One embodiment of an ADC with autonomous gain adjustment includes an ADC, a gain stage coupled to the ADC, a scaler coupled to the ADC, and a control logic that may be configured to configure the gain of the gain stage responsive to measured output of the ADC.

Analog-to-digital converters (ADCs) with background calibration processes are disclosed. In one aspect, an ADC with a plurality of comparators that each compare an input voltage to voltages that are generated at taps across a plurality of references (e.g., a reference resistor ladder). The comparators are initially calibrated with foreground calibration routines and continuously recalibrated to compensate for aging, voltage, and temperature variations without interrupting operation of the ADC by randomly taking one comparator of the plurality of comparators off-line to run calibration processes without replacing that comparator. The value for the off-line comparator may be reliably inferred from values from neighboring comparators or, in some cases, guessed randomly. While possible errors may be introduced, such errors may be driven to a mean square quantization noise level through exemplary aspects of the present disclosure.

An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.

Provided are a Time-Interleaved Successive Approximation Register Analog-to-Digital Converter, TISAR ADC, and a calibration method thereof. The calibration method for the TISAR ADC may include: sampling an analog signal input into the TISAR ADC to generate a reference digital signal (S130); according to the reference digital signal and output digital signals generated by analog-to-digital conversion sub-modules of the TISAR ADC, obtaining capacitor array calibration parameters and time delay calibration parameters of the analog-to-digital conversion sub-modules; adjusting capacitor arrays of the corresponding analog-to-digital conversion sub-modules according to the capacitor array calibration parameters, respectively; and adjusting time delays of the corresponding analog-to-digital conversion sub-modules according to the time delay calibration parameters, respectively.

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN), detecting if a binary code determined from the analog input signal (V.sub.IN) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*.sub.LSB; B*.sub.MSB), analyzing a bit of the digital signal (C.sub.OUT) and the calibration bit (B*.sub.LSB; B*.sub.MSB), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*.sub.LSB; B*.sub.MSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.