An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.

A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN), detecting if a binary code determined from the analog input signal (V.sub.IN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*.sub.RES) and a calibration bit (B*.sub.LSB), analyzing a least significant bit of the digital signal (C.sub.OUT) and the calibration bit (B*.sub.LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*.sub.LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN), detecting if a binary code determined from the analog input signal (V.sub.IN) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*.sub.LSB; B*.sub.MSB), analyzing a bit of the digital signal (C.sub.OUT) and the calibration bit (B*.sub.LSB; B*.sub.MSB), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*.sub.LSB; B*.sub.MSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

In various embodiments, at least one analog-to-digital converter (ADC) channel circuit may be used to convert an analog input signal into an output digital signal. A comparator threshold adjustment circuit may pseudorandomly modify at least one comparator threshold. A postprocessing circuit may identify, based on outputs of the ADC channel circuits, an ADC coefficient and may modify an output digital signal based on the ADC coefficient. As a result, the ADC channel circuits may more accurately convert the analog input signal into an output digital signal, as compared to a system that uses ADC channel circuits but does not include a postprocessing circuit. Further, a similar result may be obtained, as compared to a system that uses a higher gain amplifier, a higher speed amplifier, or both, but does not modify the one or more outputs.

An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals. Each of the two counters receives a respective pulse signal from the VCO and generate a digital counter value. The error generator block receives digital counter values from the two digital counters generates a digital conversion code corresponding to a difference between the digital counter values.

In one example, a circuit comprises: a current source having a current output; a switch coupled between the current output and a current terminal, the switch having a switch control input; a pulse signal generator having pulse signal outputs, the pulse signal generator configured to provide pulse signals having different pulse widths at the pulse signal outputs; and a multiplexor circuit having pulse signal inputs, a selection input and a selected pulse signal output, the selected pulse signal output coupled to the switch control input, and the pulse signal inputs coupled to the pulse signal outputs.

A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.