Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

Provided are a ramp signal calibration apparatus and method and image sensor including the apparatus. The apparatus includes: an analog-to-digital converter (ADC) including a trimmable transistor having a gain value that varies according to stored data, and configured to receive a ramp signal in a state where the gain value is a first gain value, and to output first and second output signals; a subtractor configured to calculate a difference between the first and second output signals; a digital comparator configured to compare the difference with a reference value and to determine whether a slope of the ramp signal has changed; and a counter configured to change the stored data based on whether the slope of the ramp signal has changed, wherein when the counter changes the data, the first gain value of the trimmable transistor is changed to a second gain value according to the changed data.

Representative implementations of devices and techniques provide gain calibration for analog to digital conversion of time-discrete analog inputs. An adjustable capacitance arrangement is used to reduce or eliminate gain error caused by capacitor mismatch within the ADC. For example, the capacitance arrangement may include an array of multiple switched capacitances arranged to track gain error during search algorithm operation.

The present disclosure relates to a digital-to-analog converter comprising an impedance network and a transfer function modification circuit. The transfer function modification circuit comprises a DAC and a demultiplexer. The demultiplexer may be used to selectively connect the output of the DAC to different respective nodes of the impedance network, allowing positive or negative currents to be injected into the node and modify the transfer function. By using a demultiplexer to selectively couple to different nodes, the node into which the current is injected may be modified post-manufacture, allowing transfer function modification.

A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

In some embodiments, a calibration circuit can include a first circuit configured to generate a first output voltage based on a first reference voltage, and a second circuit configured to compare the first output voltage and a second reference voltage. The calibration circuit can further include a calibration block configured to provide an adjustment to the first circuit based on the comparison of the first output voltage and the second reference voltage, with the adjustment being configured to compensate for a change in the first reference voltage. In some embodiments, such a calibration circuit can be utilized for and/or be a part of a digital-to-analog converter for wireless audio applications.

An analog-to-digital converter includes an input configuration module, an analog-to-digital conversion module, an adaptive parameter extraction module, and a full-period data restoration module. In a parameter extraction working mode, correction parameters are extracted through cooperation of the input configuration module, the analog-to-digital conversion module, the adaptive parameter extraction module, and the full-period data restoration module. In a normal working mode, digital calibration and correction of digital signals are implemented by using the analog-to-digital conversion module and the correction parameters. The correction parameters include a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.

A successive approximation ADC includes a switch circuit, a conversion circuit, a comparison circuit and a controller. The conversion circuit outputs first and second comparison voltages that are respectively equal to first and second input voltages when the switch circuit operates in an ON state. The comparison circuit compares the first and second comparison voltages to generate first and second comparison signals. Generation of least significant bits of the first and second comparison signals is related to two first capacitors and two second capacitors of the conversion circuit. When the other bits of the first comparison signal have identical logic values, the controller provides two different voltages respectively to the first capacitors and respectively to the second capacitors; and when otherwise, the controller provides one of the voltages to both of the first capacitors, and provides the other one of the voltages to both of the second capacitors.

A multi-stage pipeline successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. The processing stages quantize an analog input signal by a predetermined number of bits. A first processing stage quantizes the analog input signal and determines a first analog residue signal based on the difference between sampled instances of the analog input signal and corresponding quantized values. The subsequent stages continue this quantization, generating further analog residues by comparing sampled residues to their quantized forms. The data converter employs a sequence of operational modes to facilitate conversion of the analog input signal to a digital output signal.

An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.