Embodiments disclosed herein relate to digital signal processing, and more particularly, to detecting metastability to reduce noise and improve performance of an analog-to-digital converter (ADC). In an example, an ADC is provided that includes comparator circuitry, synchronization circuitry, digital output circuitry, and stability checking circuitry. The comparator circuitry performs a comparison of an analog input signal to an analog feedback signal and outputs a result of the comparison. The synchronization circuitry samples the result of the comparison at different times, resulting in first and second sampled values. The digital output circuitry generates a digital output signal based on the first sampled value and outputs the digital output signal. The stability checking circuitry determines whether a metastability condition occurred with respect to the analog-to-digital converter based on the first and second sampled values and outputs an indication of whether the metastability condition occurred.

A analog-to-digital conversion circuit includes a plurality of time interleaved analog-digital converters (TI-ADCs), a timing calibrator configured to calculate calibration values of the plurality of TI-ADCs based on correlation values between target samples output from target TI-ADCs and adjacent samples of adjacent TI-ADCs in two respective cycles and output codes for calibrating time skews of the plurality of TI-ADCs based on the calibration values and a plurality of calibration parameters, and a clock phase adjuster configured to adjust phases of a plurality of clock signals based on the codes.

An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.