A analog-to-digital conversion circuit includes a plurality of time interleaved analog-digital converters (TI-ADCs), a timing calibrator configured to calculate calibration values of the plurality of TI-ADCs based on correlation values between target samples output from target TI-ADCs and adjacent samples of adjacent TI-ADCs in two respective cycles and output codes for calibrating time skews of the plurality of TI-ADCs based on the calibration values and a plurality of calibration parameters, and a clock phase adjuster configured to adjust phases of a plurality of clock signals based on the codes.

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.

A processing device is built into an output device, which uses a DA converter to output a predetermined voltage value serving as a reference. The processing device includes an input voltage acquisition unit, which acquires a positive reference voltage value and a negative reference voltage value output as internal reference voltage values from an internal voltage supply in the output device. An output voltage acquisition unit acquires a positive output voltage value and a negative output voltage value output from the DA converter. An adjustment unit adjusts a set value of the DA converter and adjusts the acquired positive output voltage value and negative output voltage value toward the acquired positive reference voltage value and negative reference voltage value.

A radio frequency digital-to-analog converter comprising: a first stage converter, driven by a clock signal having a frequency F.sub.BB, configured to receive a digital baseband signal and to generate a number N parallel data streams, each having a first resolution; a serializer, driven by a clock signal having a frequency F.sub.s, configured to convert the number N parallel data streams into a serial data stream; and a second stage converter, configured to generate an analog up-converted RF signal based on the serial data stream, wherein the analog up-converted RF signal has a second resolution. The second stage converter comprises a number K slices in parallel, configured to each generate a respective portion of the analog up-converted RF signal, such that the second resolution matches the first resolution. Each slice of the number K slices comprises at least one analog delay element. F.sub.BB=F.sub.s/N; N is an integer, N>=1; K is an integer, K>=2.

A delay-domain analog-to-digital converter including a voltage-to-delay circuit and a time-to-digital converter circuit, and a method of calibrating the same. The voltage-to-delay circuit generates a delay signal based on applied calibration voltage, and the delay signal is applied to a first residue stage configured to generate a sign bit and a residue delay signal. The residue delay signal is applied to an input of a successive residue stage, which is configured to generate a sign bit and provide a residue delay signal to inputs of a next successive residue stage. First and second trim circuits are provided in a delay comparator of one of the successive residue stages, and configured to adjust a first response of the residue stage for a calibration voltage in a first range, and to adjust a second response of the residue stage for a calibration voltage in a second range.

A system includes a first digital-to-time converter (DTC) adapted to receive a first DTC code and a first clock signal. The first DTC provides an output clock signal. The system includes a calibration DTC adapted to receive a calibration DTC code and a second clock signal. The calibration DTC provides a calibration output signal. The system includes a latch comparator which provides outputs indicative of which of the output clock signal and the calibration output signal is received first. The system includes an average computation module which provides an average value of the outputs of the latch comparator. The system includes a digital controller adapted to receive the average value. The digital controller provides the DTC code and the calibration DTC code.

Disclosed are a current source array, a digital-to-analog converter, and a signal chain chip, the current source array comprising current sources each uniquely numbered and laid out in rows and columns, wherein in the first column, current source numbers for current source units in the first half of rows are determined from the row numbers, and the numbers of rows and columns, and current source numbers for current source units in the second half of rows are determined from the row numbers, the numbers of rows and columns, and current source numbers determined for the first half of rows; and current source numbers for current source units in each subsequent column are determined from current source numbers determined for the previous column, thereby forming an overall layout of current source array. Through the above re-layout of current sources, the overall area can be reduced, thus decreasing the gradient error.

A system and method for compensating segmented DAC intrinsic INL by adjusting the relative strength of DAC thermometer segments. In the method, the strength of each thermometer segment is adjusted sequentially to reduce INL to 0 at one point on each thermometer code range. The strength of the binary section is also adjusted to further reduce INL while conserving output amplitude. The system includes a calibration circuit that senses the DAC differential output and compares it to an ideal output generated from the same DAC via dithering between 0 and a maximum code. The compensation scheme only performs a specific type of DAC compensation, specifically compensating for systematic non-linearity rather than for mismatch-induced non-linearity. The method can also be applied to calibrate a full thermometer DAC.

An electronic device includes an analog computing circuit comprising a plurality of rows comprising a plurality of first rows to which a data signal for computations is input and one or more second rows to which a calibration signal for error calibration is input, and a plurality of columns connected to the plurality of rows and configured to output a computation result in which an error is calibrated, by accumulating signals transmitted from the connected plurality of rows in response to an input of the data signal and the calibration signal.

An apparatus comprises a position sensor circuit including an offset compensation circuitry to compensate for an offset voltage of a position signal. The offset compensation circuitry includes at least a first current digital-to-analog converter (DAC) and a second current DAC. The first current DAC includes a first reference input to receive a first input current that varies in response to changes in amplitude of an excitation signal. The first current DAC further includes first logic inputs to adjustably set to respective logic levels to produce a first output current to substantially match a predetermined constant current. The second current DAC includes a second reference input to receive the first output current from the first current DAC. The second current DAC further includes second logic inputs to adjustably set to respective logic levels to produce a second output current to compensate for the offset voltage.