A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.

An analog-to-digital conversion system includes: a first conversion device configured to communicate with a first analog-to-digital converter configured to convert a first analog signal into a first digital signal; a second conversion device configured to communicate with a second analog-to-digital converter configured to convert a second analog signal into a second digital signal; a first reference low power supply; and a second reference low power supply. The first conversion device is configured to correct the first digital signal, based on a variation amount of a second reference low voltage or a second reference low current. The second conversion device is configured to correct the second digital signal, based on a variation amount of a first reference low voltage or a first reference low current.

Calibration of continuous-time (CT) residue generation systems can account and compensate for mismatches in magnitude and phase that may be caused by fabrication processes, temperature, and voltage variations. In particular, calibration may be performed by providing one or more known test signals as an input to a CT residue generation system, analyzing the output of the system corresponding to the known input, and then adjusting one or more parameters of a forward and/or a feedforward path of the system so that the difference in transfer functions of these paths may be reduced/minimized. Calibrating CT residue generation systems using test signals may help decrease the magnitude of the residue signals generated by such systems, and, consequently, advantageously increase an error correction range of such systems or of further stages that may use the residue signals as input.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

According to the one embodiment, a semiconductor circuit includes: an analog-to-digital conversion circuit including a first analog-to-digital converter configured to sample at least one first sampling signal regarding an input signal based on a first clock, and a second analog-to-digital converter configured to sample at least one second sampling signal regarding the input signal based on a second clock shifted from the first clock by a first time; and a first calibration circuit configured to calibrate at least one timing of the first clock and the second clock based on a calculation result of a moving average of the first sampling signal and the second sampling signal.

Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.

In a method of operating an analog-to-digital converter, a gain error and an offset error that are associated with a digital code generated from the analog-to-digital converter are obtained by performing a first analog-to-digital conversion on a first input analog signal. The gain error and the offset error are stored. A calibration digital code is generated by performing a second analog-to-digital conversion on a second input analog signal based on the gain error and the offset error.

A current output module includes a current output section configured to output a current, an AD conversion circuit configured to convert a detection voltage, which is a voltage according to the current output from the current output section, into a digital value, a controller configured to control a current output from the current output section on the basis of the digital value of the detection voltage output from the AD conversion circuit, and a reference voltage generator configured to generate a plurality of reference voltages. The controller includes a processor configured to cause the AD conversion circuit to convert each of the plurality of reference voltages into a digital value, and a corrector configured to calibrate the AD conversion circuit on the basis of each digital value obtained by conversion of the plurality of reference voltages.

The digital temperature sensing circuit includes a temperature voltage generator configured to generate a temperature voltage varying with a temperature in response to a first reference voltage, divide a supply voltage in response to a second reference voltage, and generate a high voltage and a low voltage, a code voltage generator configured to divide the second reference voltage based on the high voltage and the low voltage and output divided voltages having different voltage levels, and a mode selector supplied with the temperature voltage and the divided voltages, and configured to output a first code or a second code in response to a mode select signal, wherein the first code and the second code have different numbers of bits.