A sound source playback unit plays back sound data from a sound source and outputs a playback signal. An amplification unit amplifies the playback signal and outputs the playback signal as an output signal converted to sound in a speaker. A fault detection unit including a first conversion circuit compares the playback signal to a predetermined first threshold, converts a waveform of the playback signal, and outputs the converted waveform as a converted playback signal. A second conversion circuit compares the output signal to a predetermined second threshold, converts a waveform of the output signal, and outputs the converted waveform as a converted output signal. A comparison circuit compares the converted playback signal to the converted output signal, and a determination circuit determines an output of the comparison circuit. Based on the determination, the fault detection unit detects a fault in the amplification unit.

In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.

The fault diagnosis circuit includes a first line including a first resistor, having one end connected to the positive (+) terminal of a battery, and having the other end connected to a first input unit of an analog to digital converter (ADC); a second line including a second resistor, having one end connected to the positive (+) terminal of the battery, and having the other end connected to a first input unit of a comparator; and a third line including a third resistor, having one end connected to the negative () terminal of the battery, having a first other end connected to a second input unit of the ADC, and having a second other end connected to a second input unit of the comparator. A fault in a battery management system can be efficiently diagnosed using a smaller number of elements.

According to embodiments, a signal processing device includes an AD converter, a memory, a prediction logic circuit, an error amount detection circuit, and a selector. The AD converter converts an input signal to an AD conversion value at a certain sampling frequency. The memory stores an AD conversion output result. The prediction logic circuit predicts a prediction value by using the AD conversion output result at the sampling frequency. The error amount detection circuit determines that there is no error in error determination of the AD conversion value when an error amount between the prediction value and the AD conversion value is smaller than a predetermined amount, and that there is an error in the error determination when the error amount is equal to or larger than the predetermined amount. The selector outputs one of the AD conversion value and the prediction value as an AD conversion output result, on the basis of the error determination.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A sampling clock generating circuit and an analog to digital converter (ADC) includes a resistance variable circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the resistance variable circuit, and the other end of the resistance variable circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.

An error compensation correction device for a pipeline analog-to-digital converter includes a correction pipeline stage and a conventional pipeline stage. For each correction pipeline stage, a corresponding error estimation circuit, a level edge detection circuit, a random level generation circuit, and MUX circuit being provided. The present disclosure can track and correct non-ideal properties and mismatching errors in real time over time along with the change of the surroundings without interrupting the ADC normal work of the pipeline. Thus the correction value is closer to the real situation.

According to embodiments, a signal processing device includes an AD converter, a memory, a prediction logic circuit, an error amount detection circuit, and a selector. The AD converter converts an input signal to an AD conversion value at a certain sampling frequency. The memory stores an AD conversion output result. The prediction logic circuit predicts a prediction value by using the AD conversion output result at the sampling frequency. The error amount detection circuit determines that there is no error in error determination of the AD conversion value when an error amount between the prediction value and the AD conversion value is smaller than a predetermined amount, and that there is an error in the error determination when the error amount is equal to or larger than the predetermined amount. The selector outputs one of the AD conversion value and the prediction value as an AD conversion output result, on the basis of the error determination.

A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.