An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.

A method for testing a DAC comprising controlling the DAC digitally to cause it to produce a known desired analogue output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

A self-healing data converter system including a data converter; a parametric function module coupled to the data converter to receive a target performance requirement for a data converter and produce a set of function values to the data converter; an assistant module that captures data converter performance under one or more stress conditions; and a processing module coupled to the data converter to stress the data converter in accordance with one or more predetermined parameters and based on the target performance requirement and data converter performance, the processing module determines new parameters based on a self-healing method and applies the new parameters to produce a new set of function values for the data converter until a predetermined threshold is met to adaptively self-heal the data converter to changed conditions.

A method for testing a DAC is provided. The method includes controlling the DAC digitally to cause it to produce a known desired analog output, for example a fixed amplitude sine wave; determining the duration of fixed voltage segments of the actual output of the DAC and using the duration of the fixed voltage segments to assess or determine performance of the DAC.

Disclosed are systems and methods for identifying and reporting failures of an analog to digital (A/D) conversion system. An A/D conversion system includes a test signal generator configured to generate a test signal including an identifiable characteristic, an A/D converter configured to convert an analog signal measured at an input of the A/D converter to a digital output, and signal injection circuitry configured to inject at least a portion of the test signal from the test signal generator as an injected signal into the analog signal using trace-to-trace crosstalk. A method includes determining whether the digital output generated by the A/D converter indicates the identifiable characteristic.

A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

A self-healing data converter system including a data converter; a parametric function module coupled to the data converter to receive a target performance requirement for a data converter and produce a set of function values to the data converter; an assistant module that captures data converter performance under one or more stress conditions; and a processing module coupled to the data converter to stress the data converter in accordance with one or more predetermined parameters and based on the target performance requirement and data converter performance, the processing module determines new parameters based on a self-healing method and applies the new parameters to produce a new set of function values for the data converter until a predetermined threshold is met to adaptively self-heal the data converter to changed conditions.

Apparatus for determining a signal-to-quantization-noise ratio of a quantization circuit includes a signal generator that generates an input test signal for input to the quantization circuit, circuitry for isolating, from output of the quantization circuit, a signal representing quantization noise, and circuitry for determining a ratio of the output of the quantization circuit to the signal representing quantization noise. The signal generator generates an analog test tone having a frequency, and the circuitry for isolating includes a notch filter filtering that frequency. Alternatively, the circuitry for isolating includes circuitry for generating a digital test signal, and a digital subtractor for subtracting the digital test signal from the output of the quantization circuit. According to another alternative, the circuitry for isolating includes a transformation circuit whose outputs represent a peak of the output of the quantization circuit and a noise floor of the output of the quantization circuit.

A FT circuit includes a distribution circuit, a number N of pipeline FT circuits, and a number M of parallel FT circuits, wherein N and M are integers greater than or equal to 2. The distribution circuit is configured to receive a plurality of samples, to divide the plurality of samples into N subsets of samples, and to forward each of the N subsets of samples to a dedicated one of the pipeline FT circuits. The pipeline FT circuits are arranged in parallel to each other and are configured to process M samples in parallel, thereby obtaining M intermediate samples per pipeline FT circuit. The pipeline FT circuits are configured to forward each of the M intermediate samples to a dedicated one of the M parallel FT circuits. Each parallel FT circuit is configured to process N intermediate samples in parallel, thereby obtaining N output samples per parallel FT circuit.

A FT circuit includes a distribution circuit, a number N of pipeline FT circuits, and a number M of parallel FT circuits, wherein N and M are integers greater than or equal to 2. The distribution circuit is configured to receive a plurality of samples, to divide the plurality of samples into N subsets of samples, and to forward each of the N subsets of samples to a dedicated one of the pipeline FT circuits. The pipeline FT circuits are arranged in parallel to each other and are configured to process M samples in parallel, thereby obtaining M intermediate samples per pipeline FT circuit. The pipeline FT circuits are configured to forward each of the M intermediate samples to a dedicated one of the M parallel FT circuits. Each parallel FT circuit is configured to process N intermediate samples in parallel, thereby obtaining N output samples per parallel FT circuit.