Disclosed examples include a method and automated test system for testing an ADC. The method includes computing an ADC noise value based on a first set of data values sampled while the ADC input terminals are shorted, computing a first system noise value based on a second set of data values sampled while a test circuit signal source applies zero volts to the ADC through a signal chain, computing a signal chain noise value based on the first system noise value and the ADC noise value, computing a measured SNR value based on a third set of data values sampled while the test circuit signal source applies a non-zero source voltage signal to the signal chain, computing a second system noise value based on the measured SNR value, and computing an ADC SNR value based on the second system noise value and the signal chain noise value.

A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.

The present disclosure discloses a method for performing an ADC phase-frequency response test including: measuring a time delay of an analog mixer and low-pass filter (MLPF) in down-converting a specific carrier frequency narrowband frequency modulation (FM) signal; determining an effective sampling frequency required by an ADC for acquiring FM signals; acquiring a high carrier frequency FM signal and a low carrier frequency FM signal before and after down-conversion is performed by the analog MLPF; and demodulating the FM signals that are acquired, correcting an initial phase of a modulation signal of the high carrier frequency FM signal and an initial phase of a modulation signal of the low carrier frequency FM signal, and calculating a phase-frequency response of the ADC at a high carrier frequency. The present disclosure has advantages of a simple test process, a wide frequency range with frequencies and a test simultaneously performed on multiple channels.

Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

A sampling circuit in a successive approximation type analog-to-digital (A/D) converting device samples a pair of analog signals constituting a differential input signal. A capacitor circuit reflects a signal level of a reference signal in the pair of analog signals through an attenuation capacitance unit and a binary capacitance unit to generate a pair of voltage signals. A comparison circuit compares the pair of voltage signals. A control circuit determines a value of each bit of a digital signal on the basis of the result of the comparison and reflects the value in the reference signal. The attenuation capacitance unit includes a fixed capacitance unit connected between a signal node at which the sampled analog signals are held and a predetermined potential node and a variable capacitance unit connected between the signal node and the predetermined potential node in parallel with the fixed capacitance unit.

Apparatus for determining a signal-to-quantization-noise ratio of a quantization circuit includes a signal generator that generates an input test signal for input to the quantization circuit, circuitry for isolating, from output of the quantization circuit, a signal representing quantization noise, and circuitry for determining a ratio of the output of the quantization circuit to the signal representing quantization noise. The signal generator generates an analog test tone having a frequency, and the circuitry for isolating includes a notch filter filtering that frequency. Alternatively, the circuitry for isolating includes circuitry for generating a digital test signal, and a digital subtractor for subtracting the digital test signal from the output of the quantization circuit. According to another alternative, the circuitry for isolating includes a transformation circuit whose outputs represent a peak of the output of the quantization circuit and a noise floor of the output of the quantization circuit.

A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as non-idealities) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.

Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.

An ADC with built-in charge-based capacitance measurements is described. An example includes a plurality of capacitors coupled in parallel to an input voltage at a common node, a plurality of drivers each coupled to a respective capacitor opposite the common node, a first switch coupled to the common node to couple the common node to a ground in response to a second clock signal from a timing generator, a second switch coupled to the common node to couple the common node to a reference voltage in response to a third clock signal from the timing generator, a successive logic circuit configured to control each driver to alternately drive the second clock signal to a selected capacitor or to couple the selected capacitor to ground, and measurement logic including a current sensor to measure a current through the common node and configured to determine a capacitance of the selected capacitor.