An analog filter, comprising, a first-time encoding machine (TEM); and a first delay element.

A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output.

Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

A signal processor apparatus includes: first and second photonic comb generators generating respective first and second combs with respective different first and second tone spacing; modulator modulating the first comb with an analog input signal; combiner combining the modulated first comb with the second comb and directing the combination results to first and second arms; spectral filter unit for each arm dividing each arm into a plurality of sub-bands; plurality of photodetectors, one for each sub-band of each arm, each photodetector outputting an electrical signal carrying information on the respective sub-band of the input signal; phase-shifter adjusting a relative phase of the first and second combs with respect to each other prior to the combiner; sensor system producing an output related to a phase difference between the first and second combs at the combiner; and controller controlling the phase-shifter based on the output of the sensor system.

The present disclosure pertains to a circuitry for processing an analog signal, wherein the circuitry is configured to generate a sample control signal depending on an energy level of the analog signal in at least one predefined frequency band, and control a sampling rate for sampling the analog signal based on the generated sample control signal.

According to one embodiment, a sensor device includes a switch, a control circuit and an A/D converter. The switch is connected to a sensor element configured to store charge and provided to read the charge stored in the sensor element from the sensor element. The control circuit is configured to control the switch so as to partially and sequentially read the charge stored in the sensor element. The A/D converter is connected to the switch, which is configured to output a digital signal obtained by A/D-converting an analog signal according to the charge, for each charge partially read via the switch.

According to the one embodiment, a semiconductor circuit includes: an analog-to-digital conversion circuit including a first analog-to-digital converter configured to sample at least one first sampling signal regarding an input signal based on a first clock, and a second analog-to-digital converter configured to sample at least one second sampling signal regarding the input signal based on a second clock shifted from the first clock by a first time; and a first calibration circuit configured to calibrate at least one timing of the first clock and the second clock based on a calculation result of a moving average of the first sampling signal and the second sampling signal.

Methods, systems, computer-readable media, and apparatuses for spurious information reduction in a data signal are presented. One example of such an apparatus includes a data converter including a plurality of analog-to-digital converters (ADCs) and configured to produce a plurality of sampled signals, a normalizer configured to obtain a plurality of common-bandwidth signals from at least the plurality of sampled signals, and a common-mode filter configured to produce a digital output signal based on the plurality of common-bandwidth signals.

A system includes a first low noise amplifier, a second low noise amplifier, a local analog oscillator signal, a signal splitter, a mixer, a mixer, an analog to digital converter and a digital channelizer. The first low noise amplifier outputs a first amplified analog signal based on a received analog antenna signal at a time t.sub.0. The second low noise amplifier outputs a second amplified analog signal based on the received analog antenna signal at a time t.sub.1. The local analog oscillator signal outputs a local analog oscillator signal. The signal splitter outputs a split analog oscillator signal and a split analog oscillator signal. The mixer outputs a first mixed signal. The mixer outputs a second mixed signal. The analog to digital converter outputs a combined digital signal. The digital channelizer outputs a received signal based on the combined digital signal.