A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the converter comprising: a signal quantizer arranged to receive the analog input signal and a threshold input and arranged to output a binary value quantized output signal based on a comparison of the input signal with the threshold signal; a plurality of samplers each arranged to sample and hold its input signal upon receipt of a trigger signal; and for each sampler: a plurality of decoders and a demultiplexer arranged to receive an output from the sampler and pass it to a selected one of said decoders based on a selector input. With a plurality of decoders associated with each of the samplers, each sampler can be re-used during the building up of the range profile.

The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

Disclosed herein is an analog-to-digital converter circuit configured for digitizing an analog input signal. The analog-to-digital converter comprises an analog input configured for receiving the analog input signal. The analog-to-digital converter circuit further comprises at least one sub-ADC connected to the analog input signal, wherein the at least one sub-ADC is configured to output at least one encoded output vector in response to receiving the analog input signal. The analog-to-digital converter circuit further comprises a lookup circuit comprising a nested lookup table. The lookup circuit is configured to select an output value from the nested lookup table using the at least one encoded output vector, wherein the lookup circuit is configured to provide the output value as the digitization of the analog input signal.

An optical sampling signal holding method for a photonic analog-to-digital conversion system, based on frequency response principles of sampling and holding, controls photoelectric conversion processes after photonic sampling to be equivalent to the signal holding effect in switch sampling, and converts sampled optical pulses into a special holding waveform, directly eliminating the time mismatch between back-end electronic analog-to-digital converters and optical pulses. The photoelectric conversion frequency responses in the invention do not lead to additional expenses on active devices and software, which greatly improves performances of the photonic analog-to-digital conversion system. The method is not limited by the number of channels, and can provide more reliable technical solutions for realizing a photonic analog-to-digital conversion system with high sampling rate in the future.

An analog-to-digital converter has a first digital signal generator that generates a first digital signal based on whether or not a sampling signal of an input signal is equal to or lower than a signal corresponding to a second reference signal higher than a first reference signal, a first slope generator to generate a first slope signal that changes with time from the sampled and held signal equal to or lower than the first reference signal, a second slope generator to generate a second slope signal that changes with time from the sampled and held signal to a signal level equal to or lower than the second reference signal, and a second digital signal generator that generates a second digital signal based on a time at which the first slope signal matches the first reference signal or a time at which the second slope signal matches the second reference signal.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.

A sampling circuit includes: a first transmission line that transmits an input signal; a second transmission line that transmits a clock signal; and a plurality of sample-hold circuits that are connected to the first and second transmission lines at a constant line distance, wherein the first transmission line transmits the input signal at a first propagation time for each of the line distances, and the second transmission line transmits the clock signal at a second propagation time that is a sum of a preset sampling interval and the first propagation time for each of the line distances.

An ADC sampling data identification method and system, integrated circuit and decoding device are disclosed. The ADC sampling data identification method includes in the integrated circuit, converting sampling data from n time interleaved ADC chips into serial data, generating a preamble sequence, combining the serial data with the generated preamble sequence to obtain new serial data, sending the new serial data to a decoding device, generating a clock signal that matches the new serial data, and sending the clock signal to the decoding device; and in the decoding device, receiving the new serial data and the clock signal from the ADC integrated circuit, obtaining the preamble sequence for combining according to an agreement with the ADC integrated circuit, and identifying a start position of the sampling data from the time interleaved ADC chips.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

A wide-band analog input signal is converted into a digital output signal on the basis of a band division method without the need for filter circuits. An analog processing block A.sub.j (j=2 to N, where N is an integer) down-converts an analog input signal S.sub.x using a cutoff frequency fj-1 of a channel CH.sub.j-1 and A/D-converts an analog signal S.sub.aj acquired as a result. A digital processing block B.sub.j doubles the signal strength of a first digital signal S.sub.1j acquired by A.sub.j, subtracts a third digital signal S.sub.3j-1 of the channel CH.sub.j-1 from a second digital signal S.sub.2j acquired as a result, up-converts the acquired third digital signal S.sub.3j using the cutoff frequency f.sub.j-1, and outputs the result to an adder as a channel output signal S.sub.yj of a corresponding channel CH.sub.j.