A broadband digitizer for an applied broadband analog input signal SA(t). The digitizer includes a low frequency analog-to-digital converter (LF ADC) channel and a high frequency analog-to-digital converter (HF ADC) channel, an input splitter coupled to respective inputs to the LF ADC channel HF ADC channels, a frequency divider, and a combining unit. Low frequency portions of SA(t) are digitized to digital signal SD.sub.LF[n] in the LF ADC channel and high frequency portions of SA(t) are digitized to digital signal SD.sub.HF[n] in the HF ADC channel. The combining unit combines the digital signals SD.sub.LF[n] and SD.sub.HF[n] to form distortion-reduced SD[n], corresponding to SA(t). Front ends of the LF ADC channel and HF ADC channel reduce level-caused distortions, and the combining unit reduces ADC frequency-caused, time-position-caused, and interpolation-caused distortions.

Provided are an apparatus and a method for measuring a frequency of a broadband signal by using low-speed ADCs having sub-Nyquist sampling rates. A plurality of channels each including a low-speed ADC having a sub-Nyquist sampling rate (e.g. sampling frequency from several MHz to hundreds of MHz) are provided, and the frequency of an input signal corresponding to a combination of frequencies calculated through the respective channels is estimated. Therefore, as the number of channels increases, the range of measurable frequencies may be extended.

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

A measurement circuit comprises an electronic circuit, multiple measurement channels, and a combining circuit. The electronic circuit includes a first terminal, a second terminal, and a non-resistive circuit element. Each of the multiple measurement channels includes a differential input connected to the electronic circuit. The differential inputs of the multiple measurement channels are connected in series and include a differential input coupled to the non-resistive circuit element. One input of a differential input of a first measurement channel of the multiple measurement channels is connected to the first terminal of the electronic circuit and one input of a differential input of a second measurement channel of the multiple measurement channels is connected to the second terminal of the electronic circuit. The combining circuit receives multiple outputs from the multiple measurement channels and produce a composite output signal.

A receiver module for receiving an electromagnetic signal, including an analog frontend and at least a first receiving channel and a second receiving channel is described. The receiving channels are both connected to the analog frontend, wherein the frontend is configured to receive an input signal including a symbol sequence and to forward the input signal to the receiving channels, wherein the receiving channels each include an analog to digital converter, wherein the second receiving channel includes an attenuator, wherein the first receiving channel and the second receiving channel each include a soft-input-soft-output-decoder, and wherein the soft-input-soft-output decoders each are configured to process the symbol sequence. Moreover, a data transmission system and a method for receiving an electromagnetic signal are described.

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

A circuit arrangement includes a microcontroller having a first analog-to-digital converter whose input is connected to the output of a first multiplexer whose output is connected to a first comparison device for comparing reference voltages, and a first serial interface circuit connected to the first comparison device. A voltage generating circuit includes a second analog-to-digital converter whose input is connected to the output of a second multiplexer whose output is connected to a number of registers, which are connected to a safety value generator and store digital values together with a respective safety value, and a second serial interface circuit connected to the registers. The first and second serial interface circuits are connected to each other for communication of the microcontroller with the voltage generating circuit, the first interface circuit being connected to a second comparison device for comparing supply voltages and/or currents with desired voltages and/or desired currents.

Provided are an apparatus and a method for measuring a frequency of a broadband signal by using low-speed ADCs having sub-Nyquist sampling rates. A plurality of channels each including a low-speed ADC having a sub-Nyquist sampling rate (e.g. sampling frequency from several MHz to hundreds of MHz) are provided, and the frequency of an input signal corresponding to a combination of frequencies calculated through the respective channels is estimated. Therefore, as the number of channels increases, the range of measurable frequencies may be extended.

A time interleaved ADC includes sub-ADCs that sample an analog input signal at a timing synchronized with a clock signal to convert the analog input signal into a digital output signal, delay circuits that apply a time difference to the analog input signal such that the analog input signal is input to each of the sub-ADCs with a delay of a first delay time in an arrangement order of the sub-ADCs, and delay circuits that apply a time difference to the clock signal such that the clock signal is input to each of the sub-ADCs with a delay of a second delay time in the arrangement order of the sub-ADCs.