An analog-digital conversion apparatus includes: an analog-digital converter (ADC) included in an integrated circuit (IC) and configured to operate based on a sampling clock constituting a portion of a plurality of clocks; and a driver included in the IC and configured to operate based on another portion of the plurality of clocks, and produce a driving signal based on a digital value output from the ADC. The ADC and the driver are synchronized with each other based on an interrupt request (Irq) of the IC.

An integrated circuit includes a multiplexer circuit configured to provide an output signal on a conductive line, a programmable gain amplifier having a non-inverting input connected to the conductive line to receive the output signal from the multiplexer, a slew rate adjust circuit connected at a first node on the conductive line between the multiplexer circuit and the programmable gain amplifier, a first switch including a first terminal connected to the first node and a second terminal connected to the input of the programmable gain amplifier, and a low pass filter connected between the first and second terminals of the first switch.

A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.

An AD converter includes a plurality of analog input terminals, a reference signal generation circuit that generates an analog reference signal, a sample-and-hold unit that includes a plurality of sample-and-hold circuits sampling the analog reference signal or one of analog input signals from the analog input terminals, a control unit that controls the sample-and-hold unit, and a conversion unit that converts an output signal from the sample-and-hold unit into a digital signal. The control unit controls the sample-and-hold unit to perform the output operation for analog input signal and the sampling operation for the analog reference signal.

A system includes a control circuit and an adjustable low-pass filter. The control circuit is configured to receive an input signal and to control at least one engine output based on the input signal. The adjustable low-pass filter receives the input signal, and filters the input signal prior to forwarding the input signal to the control circuit. The adjustable low-pass filter has a first setting in which the adjustable low-pass filter has a first cut-off frequency and a second setting in which the adjustable low-pass filter has a second cut-off frequency. The first setting configures the control circuit to be used with a first sensor having a first dynamic range and the second setting configures the control circuit to be used with a second sensor having a second dynamic range.

A system and method for detection of an event and recording data associated with the event. An application-specific integrated circuit (ASIC) for event-driven data acquisition from detector is disclosed. The event-driven circuitry stays silent when there is no event detected on the detector. The event-driven data acquisition system consumes small power and may consume no memory during waiting for an event. Once the event arrives (e.g. photons, particle or ion hits the detector panel), the event is detected and recorded. The ASIC includes multi-channel ADCs (or ADC arrays) with flexible resolution which enables an option to operate at a lower resolution during the silent period to save power.

The present invention relates to an incremental analog to digital converter incorporating noise shaping and residual error quantization. In one embodiment, a circuit includes an incremental analog to digital converter, comprising a loop filter that filters an analog input signal in response to receiving a reset signal, resulting in a filtered analog input signal, and a successive approximation register (SAR) quantizer, coupled with the filtered analog input signal, that converts the filtered analog input signal to an intermediate digitized output of a first resolution based on a reference voltage, wherein the SAR quantizer comprises a feedback loop that shapes quantization noise generated by the SAR quantizer as a result of converting the filtered analog input signal; and a digital filter, coupled with the intermediate digitized output, that generates a digitized output signal of a second resolution, greater than the first resolution, by digitally filtering the intermediate digitized output.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, and MACs. Typically, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, and MACs increase, usually the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications. Moreover, the multipliers and MACs disclosed in this invention can be placed near conventional CMOS memory cells, such as Static-Random-Access-Memory (SRAM) or Electrically Programmable Read-Only Memory (EPROM) or Electrically Erasable Programmable Read-Only Memory (E.sup.2PROM), which facilitates In-Memory-Compute (IMC) and or near-memory-compute (NMC), that can further reduce dynamic power consumption.

A machine learning (ML)-based phase current balancer for a multiphase power converter includes one or more inputs, one or more outputs, and an artificial neural network. The artificial neural network includes a plurality of artificial neurons and is trained to provide corrective phase current imbalance information at the one or more outputs for correcting phase current imbalance within the multiphase power converter, based on information available at the one or more inputs and indicative of individual phase currents of the multiphase power converter.

A circuit arrangement includes a microcontroller having a first analog-to-digital converter whose input is connected to the output of a first multiplexer whose output is connected to a first comparison device for comparing reference voltages, and a first serial interface circuit connected to the first comparison device. A voltage generating circuit includes a second analog-to-digital converter whose input is connected to the output of a second multiplexer whose output is connected to a number of registers, which are connected to a safety value generator and store digital values together with a respective safety value, and a second serial interface circuit connected to the registers. The first and second serial interface circuits are connected to each other for communication of the microcontroller with the voltage generating circuit, the first interface circuit being connected to a second comparison device for comparing supply voltages and/or currents with desired voltages and/or desired currents.